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| author | Michael Tokarev <mjt@tls.msk.ru> | 2023-08-23 09:53:15 +0300 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-08-31 19:47:43 +0200 |
| commit | d02d06f8f1299eb7a4422c283b9b9cbb4deb0cf9 (patch) | |
| tree | 396261997085669c567a753c6fc50dbf250fff09 /util/cpuinfo-i386.c | |
| parent | c342a5d38c7e15b8bf2c13431b09af32041012c4 (diff) | |
| download | focaccia-qemu-d02d06f8f1299eb7a4422c283b9b9cbb4deb0cf9.tar.gz focaccia-qemu-d02d06f8f1299eb7a4422c283b9b9cbb4deb0cf9.zip | |
util: spelling fixes
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230823065335.1919380-3-mjt@tls.msk.ru> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'util/cpuinfo-i386.c')
| -rw-r--r-- | util/cpuinfo-i386.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/util/cpuinfo-i386.c b/util/cpuinfo-i386.c index 3a7b7e0ad1..b2ed65bb10 100644 --- a/util/cpuinfo-i386.c +++ b/util/cpuinfo-i386.c @@ -1,6 +1,6 @@ /* * SPDX-License-Identifier: GPL-2.0-or-later - * Host specific cpu indentification for x86. + * Host specific cpu identification for x86. */ #include "qemu/osdep.h" @@ -74,7 +74,7 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) * of their memory operands to be 16-byte aligned. * * AMD has provided an even stronger guarantee that processors - * with AVX provide 16-byte atomicity for all cachable, + * with AVX provide 16-byte atomicity for all cacheable, * naturally aligned single loads and stores, e.g. MOVDQU. * * See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688 |