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| author | Tim 'mithro' Ansell <mithro@mithis.com> | 2017-04-18 16:15:51 +1000 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2017-04-21 23:56:00 +0900 |
| commit | 3fee028d1ea02cd16470dc5c65d54974ef85b673 (patch) | |
| tree | a3c5ffc541f87d3ca753306e83d7999bb23fc2a8 /util/qemu-progress.c | |
| parent | 356a2db3c6f84e8e79e5afa3913514184bff5f50 (diff) | |
| download | focaccia-qemu-3fee028d1ea02cd16470dc5c65d54974ef85b673.tar.gz focaccia-qemu-3fee028d1ea02cd16470dc5c65d54974ef85b673.zip | |
target/openrisc: Implement EPH bit
Exception Prefix High (EPH) control bit of the Supervision Register (SR). The significant bits (31-12) of the vector offset address for each exception depend on the setting of the Supervision Register (SR)'s EPH bit and the Exception Vector Base Address Register (EVBAR). If SR[EPH] is set, the vector offset is logically ORed with the offset 0xF0000000. This means if EPH is; * 0 - Exceptions vectors start at EVBAR * 1 - Exception vectors start at EVBAR | 0xF0000000 Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com> Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'util/qemu-progress.c')
0 files changed, 0 insertions, 0 deletions