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* system/physmem: Extract API out of 'system/ram_addr.h' headerPhilippe Mathieu-Daudé2025-10-071-0/+1
| | | | | | | | | | Very few files use the Physical Memory API. Declare its methods in their own header: "system/physmem.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Cédric Le Goater <clg@redhat.com> Message-Id: <20251001175448.18933-19-philmd@linaro.org>
* system/physmem: Drop 'cpu_' prefix in Physical Memory APIPhilippe Mathieu-Daudé2025-10-071-6/+6
| | | | | | | | | | | The functions related to the Physical Memory API declared in "system/ram_addr.h" do not operate on vCPU. Remove the 'cpu_' prefix. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Cédric Le Goater <clg@redhat.com> Message-Id: <20251001175448.18933-18-philmd@linaro.org>
* include/hw/core/cpu: Introduce cpu_tlb_fastRichard Henderson2025-09-231-8/+8
| | | | | | | | Encapsulate access to cpu->neg.tlb.f[] in a function. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* include/hw/core/cpu: Introduce MMUIdxMapRichard Henderson2025-09-231-15/+15
| | | | | | | | | Use a typedef instead of uint16_t directly when describing sets of mmu indexes. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Assert TCGCPUOps.pointer_wrap is setRichard Henderson2025-05-281-5/+2
| | | | | | | | All targets now provide the function, so we can make the call unconditional. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target: Use cpu_pointer_wrap_uint32 for 32-bit targetsRichard Henderson2025-05-281-0/+6
| | | | | | | | | | | | | | | | | M68K, MicroBlaze, OpenRISC, RX, TriCore and Xtensa are all 32-bit targets. AVR is more complicated, but using a 32-bit wrap preserves current behaviour. Cc: Michael Rolnik <mrolnik@gmail.com> Cc: Laurent Vivier <laurent@vivier.eu> Cc: Stafford Horne <shorne@gmail.com> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: Max Filippov <jcmvbkbc@gmail.com> Tested-by Bastian Koppelmann <kbastian@mail.uni-paderborn.de> (tricore) Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target: Use cpu_pointer_wrap_notreached for strict align targetsRichard Henderson2025-05-281-0/+13
| | | | | | | | | | Alpha, HPPA, and SH4 always use aligned addresses, and therefore never produce accesses that cross pages. Cc: Helge Deller <deller@gmx.de> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Add TCGCPUOps.pointer_wrapRichard Henderson2025-05-281-0/+6
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Fix atomic_mmu_lookup vs TLB_FORCE_SLOWRichard Henderson2025-05-281-7/+8
| | | | | | | | | | | | When we moved TLB_MMIO and TLB_DISCARD_WRITE to TLB_SLOW_FLAGS_MASK, we failed to update atomic_mmu_lookup to properly reconstruct flags. Fixes: 24b5e0fdb543 ("include/exec: Move TLB_MMIO, TLB_DISCARD_WRITE to slow flags") Reported-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Build cputlb.c onceRichard Henderson2025-05-051-1/+2
| | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Use target_long_bits() in cputlb.cRichard Henderson2025-05-051-12/+13
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* include: Remove 'exec/exec-all.h'Philippe Mathieu-Daudé2025-04-301-1/+0
| | | | | | | | | | | | | "exec/exec-all.h" is now fully empty, let's remove it. Mechanical change running: $ sed -i '/exec\/exec-all.h/d' $(git grep -wl exec/exec-all.h) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250424202412.91612-14-philmd@linaro.org>
* accel/tcg: Extract probe API out of 'exec/exec-all.h'Philippe Mathieu-Daudé2025-04-301-0/+1
| | | | | | | | | | | Declare probe methods in "accel/tcg/probe.h" to emphasize they are specific to TCG accelerator. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250424202412.91612-13-philmd@linaro.org>
* physmem: Restrict TCG IOTLB code to TCG accelPhilippe Mathieu-Daudé2025-04-301-0/+1
| | | | | | | | | | | Restrict iotlb_to_section(), address_space_translate_for_iotlb() and memory_region_section_get_iotlb() to TCG. Declare them in the new "accel/tcg/iommu.h" header. Declare iotlb_to_section() using the MemoryRegionSection typedef. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250424202412.91612-12-philmd@linaro.org>
* accel/tcg: Merge internal-target.h into internal-common.hRichard Henderson2025-04-301-1/+0
| | | | | | | | | There's nothing left in internal-target.h that is target specific. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Add CPUState arg to tb_invalidate_phys_range_fastRichard Henderson2025-04-301-1/+1
| | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Move cpu_req_mo() macro to target-agnostic 'backend-ldst.h'Philippe Mathieu-Daudé2025-04-231-0/+1
| | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Propagate CPUState argument to cpu_req_mo()Philippe Mathieu-Daudé2025-04-231-10/+10
| | | | | | | | | In preparation of having tcg_req_mo() access CPUState in the next commit, pass it to cpu_req_mo(), its single caller. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* exec: Restrict 'cpu_ldst.h' to accel/tcg/Philippe Mathieu-Daudé2025-04-231-1/+1
| | | | | | | | | | | | Mechanical change using: $ sed -i -e 's,exec/cpu_ldst,accel/tcg/cpu-ldst,' \ $(git grep -l exec/cpu_ldst.h) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* page-vary: Restrict scope of TARGET_PAGE_BITS_MINRichard Henderson2025-04-231-1/+0
| | | | | | | | | | The only place we really need to know the minimum is within page-vary-target.c. Rename the target/arm TARGET_PAGE_BITS_MIN to TARGET_PAGE_BITS_LEGACY to emphasize what it really means. Move the assertions related to minimum page size as well. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* include/exec: Redefine tlb-flags with absolute valuesRichard Henderson2025-04-231-0/+2
| | | | | | | | | | | Don't base the values on TARGET_PAGE_BITS_MIN, but do verify that TLB_FLAGS_MASK does not overlap minimum page size. All targets now have the same placement for these flags, simplifying mmu management when we enable heterogeneous systems. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Split out tlb-bounds.hRichard Henderson2025-04-231-0/+1
| | | | | | | | | The CPU_TLB_DYN_{MIN,MAX}_BITS definitions are not required outside of cputlb.c and translate-all.c. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Rebuild full flags in tlb_reset_dirty_range_lockedRichard Henderson2025-04-231-2/+3
| | | | | | | Undo the split between inline and slow flags before masking. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Pass CPUTLBEntryFull to tlb_reset_dirty_range_lockedRichard Henderson2025-04-231-10/+10
| | | | | | | | | | While we're renaming things, don't modify addr; save it for reuse in the qatomic_set. Compute the host address into a new local variable. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Fix argument types of tlb_reset_dirtyRichard Henderson2025-04-231-3/+3
| | | | | | | | | | | The arguments to tlb_reset_dirty are host pointers. The conversion from ram_addr_t was done in the sole caller, tlb_reset_dirty_range_all. Fixes: e554861766d ("exec: prepare for splitting") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* exec/cpu-all: extract tlb flags defines to exec/tlb-flags.hPierrick Bouvier2025-04-231-0/+1
| | | | | | | Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250320223002.2915728-3-pierrick.bouvier@linaro.org>
* accel/tcg: Remove unnecesary inclusion of memory-internal.h in cputlb.cPhilippe Mathieu-Daudé2025-04-231-1/+0
| | | | | | | | | | | At some point cputlb.c stopped depending on the "exec/memory-internal.h" header. Clean that now. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250317161329.40300-2-philmd@linaro.org>
* include/system: Move exec/ram_addr.h to system/ram_addr.hRichard Henderson2025-04-231-1/+1
| | | | | | | | Convert the existing includes with sed. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* include/system: Move exec/memory.h to system/memory.hRichard Henderson2025-04-231-1/+1
| | | | | | | | | | | | Convert the existing includes with sed -i ,exec/memory.h,system/memory.h,g Move the include within cpu-all.h into a !CONFIG_USER_ONLY block. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* include/exec: Inline *_code memory operationsRichard Henderson2025-04-231-28/+0
| | | | | | | | | These need to be per-target for 'abi_ptr' and endianness. These expand inline to the *_mmu api with a lookup of the target's cpu_mmu_index() and ra == 0. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* include/exec: Use vaddr for *_mmu guest memory access routinesRichard Henderson2025-04-231-4/+4
| | | | | | | | Use vaddr only for the newest api, because it has the least number of uses and therefore is the easiest to audit. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* exec: Declare tlb_hit*() in 'exec/cputlb.h'Philippe Mathieu-Daudé2025-03-081-0/+23
| | | | | | | | | Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20241114011310.3615-20-philmd@linaro.org>
* accel/tcg: Rename 'hw/core/tcg-cpu-ops.h' -> 'accel/tcg/cpu-ops.h'Philippe Mathieu-Daudé2025-03-061-1/+1
| | | | | | | | | | | | | | TCGCPUOps structure makes more sense in the accelerator context rather than hardware emulation. Move it under the accel/tcg/ scope. Mechanical change doing: $ sed -i -e 's,hw/core/tcg-cpu-ops.h,accel/tcg/cpu-ops.h,g' \ $(git grep -l hw/core/tcg-cpu-ops.h) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-11-philmd@linaro.org>
* include/exec: Use uintptr_t in CPUTLBEntryRichard Henderson2025-02-181-17/+4
| | | | | | | | | Since we no longer support 64-bit guests on 32-bit hosts, we can use a 32-bit type on a 32-bit host. This shrinks the size of the structure to 16 bytes on a 32-bit host. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_pageRichard Henderson2025-02-181-2/+2
| | | | | | The declarations use vaddr for size. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove TCG_OVERSIZED_GUESTRichard Henderson2025-02-181-7/+0
| | | | | | | This is now prohibited in configuration. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Move TranslationBlock declarations to 'tb-internal.h'Philippe Mathieu-Daudé2024-12-201-0/+1
| | | | | | | | | | Move declarations related to TranslationBlock out of the generic "internal-target.h" to "tb-internal.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-11-philmd@linaro.org>
* accel/tcg: Move 'exec/translate-all.h' -> 'tb-internal.h'Philippe Mathieu-Daudé2024-12-201-1/+1
| | | | | | | | | | "exec/translate-all.h" is only useful to TCG accelerator, so move it to accel/tcg/, after renaming it 'tb-internal.h'. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-9-philmd@linaro.org>
* accel/tcg: Have tlb_vaddr_to_host() use vaddr typePhilippe Mathieu-Daudé2024-12-201-1/+1
| | | | | | | | | | | | | abi_ptr is expected to be used in user emulation. tlb_vaddr_to_host() uses it, but can be used in system emulation. Replace the type by 'vaddr' which is equivalent on user emulation but also works on system. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241114011310.3615-13-philmd@linaro.org>
* accel/tcg: Use the alignment test in tlb_fill_alignRichard Henderson2024-10-131-43/+45
| | | | | | | | | When we have a tlb miss, defer the alignment check to the new tlb_fill_align hook. Move the existing alignment check so that we only perform it with a tlb hit. Reviewed-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Add TCGCPUOps.tlb_fill_alignRichard Henderson2024-10-131-23/+38
| | | | | | | | | | | | | | | | | Add a new callback to handle softmmu paging. Return the page details directly, instead of passing them indirectly to tlb_set_page. Handle alignment simultaneously with paging so that faults are handled with target-specific priority. Route all calls of the two hooks through a tlb_fill_align function local to cputlb.c. As yet no targets implement the new hook. As yet cputlb.c does not use the new alignment check. Reviewed-by: Helge Deller <deller@gmx.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* include/exec/memop: Introduce memop_atomicity_bitsRichard Henderson2024-10-131-14/+2
| | | | | | | | | Split out of mmu_lookup. Reviewed-by: Helge Deller <deller@gmx.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* include/exec/memop: Rename get_alignment_bitsRichard Henderson2024-10-131-2/+2
| | | | | | | | | | Rename to use "memop_" prefix, like other functions that operate on MemOp. Reviewed-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Assert noreturn from write-only page for atomicsRichard Henderson2024-10-131-3/+2
| | | | | | | | | There should be no "just in case"; the page is already in the tlb, and known to be not readable. Reviewed-by: Helge Deller <deller@gmx.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/cputlb: remove other-cpu capability from TLB flushingNicholas Piggin2024-05-241-33/+9
| | | | | | | | | | | | | Some TLB flush operations can flush other CPUs. The problem with this is they used non-synced variants of flushes (i.e., that return before the destination has completed the flush). Since all TLB flush users need the _synced variants, and that last user (ppc) of the non-synced flush was buggy, this is a footgun waiting to go off. There do not seem to be any callers that flush other CPUs, so remove the capability. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
* tcg/cputlb: Remove non-synced variants of global TLB flushesNicholas Piggin2024-05-241-103/+0
| | | | | | | | | | | | | | | | | These are no longer used. tlb_flush_all_cpus: removed by previous commit. tlb_flush_page_all_cpus: removed by previous commit. tlb_flush_page_bits_by_mmuidx_all_cpus: never used. tlb_flush_page_by_mmuidx_all_cpus: never used. tlb_flush_page_bits_by_mmuidx_all_cpus: never used, thus: tlb_flush_range_by_mmuidx_all_cpus: never used. tlb_flush_by_mmuidx_all_cpus: never used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
* exec/cpu: Extract page-protection definitions to page-protection.hPhilippe Mathieu-Daudé2024-05-061-0/+1
| | | | | | | | | | | | | | | | Extract page-protection definitions from "exec/cpu-all.h" to "exec/page-protection.h". The list of files requiring the new header was generated using: $ git grep -wE \ 'PAGE_(READ|WRITE|EXEC|RWX|VALID|ANON|RESERVED|TARGET_.|PASSTHROUGH)' Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Nicholas Piggin <npiggin@gmail.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-3-philmd@linaro.org>
* exec: Move CPUTLBEntry helpers to cputlb.cPhilippe Mathieu-Daudé2024-04-261-0/+51
| | | | | | | | | | | | | | | The following CPUTLBEntry helpers are only used in accel/tcg/cputlb.c: - tlb_index() - tlb_entry() - tlb_read_idx() - tlb_addr_write() Move them to this file, allowing to remove the huge "cpu.h" header inclusion from "exec/cpu_ldst.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240418192525.97451-13-philmd@linaro.org>
* exec: Reduce tlb_set_dirty() declaration scopePhilippe Mathieu-Daudé2024-04-261-1/+1
| | | | | | | | | | | tlb_set_dirty() is only used in accel/tcg/cputlb.c, where it is defined. Declare it statically, removing the stub. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240418192525.97451-11-philmd@linaro.org>
* accel/tcg: Add TLB_CHECK_ALIGNEDRichard Henderson2024-03-051-3/+27
| | | | | | | | | This creates a per-page method for checking of alignment. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240301204110.656742-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>