summary refs log tree commit diff stats
path: root/disas/riscv.c (follow)
Commit message (Expand)AuthorAgeFilesLines
* target/riscv: honour show_opcodes when disassemblingAlex Bennée2024-03-061-13/+15
* disas/riscv: Add amocas.[w,d,q] instructionsRob Bradford2024-01-101-0/+9
* disas/riscv: Replace TABs with spaceMax Chou2023-11-071-3/+3
* disas/riscv: Add support for vector crypto extensionsMax Chou2023-11-071-0/+137
* disas/riscv: Add rv_codec_vror_vi for vror.viMax Chou2023-11-071-1/+13
* disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14Alvin Chang2023-10-121-2/+2
* riscv/disas: Fix disas output of upper immediatesChristoph Müllner2023-07-191-3/+16
* riscv: Add support for the Zfa extensionChristoph Müllner2023-07-101-0/+139
* target/riscv: Add disas support for BF16 extensionsWeiwei Li2023-07-101-0/+44
* disas/riscv: Add support for XThead* instructionsChristoph Müllner2023-07-101-0/+69
* disas/riscv: Add support for XVentanaCondOpsChristoph Müllner2023-07-101-0/+4
* disas/riscv: Provide infrastructure for vendor extensionsChristoph Müllner2023-07-101-2/+26
* disas/riscv: Encapsulate opcode_data into decodeChristoph Müllner2023-07-101-1/+8
* disas/riscv: Make rv_op_illegal a shared enum valueChristoph Müllner2023-07-101-1/+1
* disas/riscv: Move types/constants to new header fileChristoph Müllner2023-07-101-269/+1
* disas/riscv.c: Remove redundant parenthesesWeiwei Li2023-06-131-109/+110
* disas/riscv.c: Fix lines with over 80 charactersWeiwei Li2023-06-131-61/+140
* disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructionsWeiwei Li2023-06-131-370/+370
* disas/riscv.c: Support disas for Z*inx extensionsWeiwei Li2023-06-131-4/+12
* disas/riscv.c: Support disas for Zcm* extensionsWeiwei Li2023-06-131-1/+7
* target/riscv: Pass RISCVCPUConfig as target_info to disassemble_infoWeiwei Li2023-06-131-3/+7
* disas/riscv: Decode czero.{eqz,nez}Richard Henderson2023-05-251-0/+6
* disas/riscv.c: add disasm support for Zc*Weiwei Li2023-05-051-1/+227
* Fix incorrect register name in disassembler for fmv,fabs,fneg instructionsMikhail Tyutin2023-03-141-9/+10
* disas/riscv: Fix slli_uw decodingIvan Klokov2023-03-141-4/+4
* disas/riscv Fix ctzw disassembleIvan Klokov2023-03-051-1/+1
* target/riscv: update disas.c for xnor/orn/andn and slli.uwPhilipp Tomsich2023-02-071-4/+4
* disas/riscv.c: rvv: Add disas support for vector instructionsYang Liu2022-10-141-2/+1430
* target/riscv: Remove sideleg and sedelegRahul Pathak2022-09-271-2/+0
* target/riscv: fix shifts shamt value for rv128cFrédéric Pétrot2022-09-071-6/+21
* disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructionsWeiwei Li2022-04-291-1/+172
* target/riscv: setup everything for rv64 to support rv128 executionFrédéric Pétrot2022-01-081-0/+5
* disas/riscv: Add Zb[abcs] instructionsPhilipp Tomsich2021-10-071-3/+154
* disas/riscv: Fix `rdinstreth` constraintWladimir J. van der Laan2019-06-271-2/+3
* disas/riscv: Disassemble reserved compressed encodings as illegalMichael Clark2019-06-271-17/+45
* disas: Rename include/disas/bfd.h back to include/disas/dis-asm.hMarkus Armbruster2019-04-181-1/+1
* RISC-V: Remove unnecessary disassembler constraintsMichael Clark2019-03-191-138/+0
* RISC-V: Fix missing break statement in disassemblerMichael Clark2018-05-061-1/+2
* RISC-V: Include instruction hex in disassemblyMichael Clark2018-05-061-19/+20
* RISC-V: Fix incorrect disassembly for addiwMichael Clark2018-03-281-1/+1
* RISC-V DisassemblerMichael Clark2018-03-071-0/+3048