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path: root/hw/intc/arm_gicv3_dist.c (follow)
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* hw/intc/arm_gicv3: Implement GICD_INMIRJinjie Ruan2024-04-251-0/+34
* hw/intc/arm_gicv3: Add has-nmi property to GICv3 deviceJinjie Ruan2024-04-251-0/+2
* bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plxPhilippe Mathieu-Daudé2023-01-181-4/+4
* hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisementLuke Starrett2022-12-151-2/+2
* Fix 'writeable' typosPeter Maydell2022-06-081-1/+1
* hw/intc/arm_gicv3: Update ID and feature registers for GICv4Peter Maydell2022-04-221-3/+4
* hw/intc/arm_gicv3: Report correct PIDR0 values for ID registersPeter Maydell2022-04-221-1/+1
* hw/intc/arm_gicv3: Fix missing spaces in error log messagesPeter Maydell2022-03-071-2/+2
* hw/intc: GICv3 ITS Feature enablementShashi Mallela2021-09-131-1/+4
* hw/intc/arm_gicv3: Replace mis-used MEMTX_* constants by booleansPhilippe Mathieu-Daudé2021-09-011-95/+106
* hw/intc/arm_gicv3_dist: Rename 64-bit accessors with 'q' suffixPhilippe Mathieu-Daudé2021-09-011-6/+6
* hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1Peter Maydell2019-06-171-1/+7
* hw/intc/arm_gicv3: Fix decoding of ID register rangePeter Maydell2019-06-171-2/+2
* hw/intc/arm_gicv3: fix an extra left-shift when reading IPRIORITYRAmol Surati2018-06-221-1/+2
* hw/intc/arm_gicv3: Make reserved register addresses RAZ/WIPeter Maydell2018-01-111-0/+13
* hw/intc/arm_gicv3: Fix compilation with simple trace backendPeter Maydell2016-06-201-0/+1
* hw/intc/arm_gicv3: Implement gicv3_set_irq()Peter Maydell2016-06-171-0/+21
* hw/intc/arm_gicv3: Implement GICv3 distributor registersShlomo Pongratz2016-06-171-0/+858