| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | hw, target: Add ResetType argument to hold and exit phase methods | Peter Maydell | 2024-04-25 | 1 | -2/+2 |
| * | bulk: Access existing variables initialized to &S->F when available | Philippe Mathieu-Daudé | 2024-03-12 | 1 | -1/+1 |
| * | hw/cxl: Standardize all references on CXL r3.1 and minor updates | Jonathan Cameron | 2024-02-14 | 1 | -2/+2 |
| * | hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExt | Jonathan Cameron | 2023-11-07 | 1 | -1/+1 |
| * | hw/pci-bridge/cxl_root_port: Wire up MSI | Jonathan Cameron | 2023-03-07 | 1 | -0/+61 |
| * | hw/pci-bridge/cxl_root_port: Wire up AER | Jonathan Cameron | 2023-03-07 | 1 | -0/+3 |
| * | pci: Convert child classes of TYPE_PCIE_ROOT_PORT to 3-phase reset | Peter Maydell | 2022-12-16 | 1 | -5/+9 |
| * | hw/cxl/rp: Add a root port | Ben Widawsky | 2022-05-13 | 1 | -0/+236 |