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path: root/hw/pci-bridge/cxl_upstream.c (follow)
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* hw/cxl/cxl-cdat: Make cxl_doe_cdat_init() return booleanZhao Liu2024-04-251-2/+1
* hw/pci-bridge/cxl_upstream: Fix missing ERRP_GUARD() in cxl_usp_realize()Zhao Liu2024-03-121-0/+1
* hw/pci-bridge/cxl_upstream: Fix problem with g_steal_pointer()Thomas Huth2024-03-091-4/+4
* hw/cxl: Standardize all references on CXL r3.1 and minor updatesJonathan Cameron2024-02-141-2/+2
* hw/pci-bridge/cxl_upstream: Drop g_malloc() failure handlingJonathan Cameron2024-02-141-6/+0
* hw/pci-bridge/cxl_upstream: Move defintion of device to header.Jonathan Cameron2023-11-071-10/+1
* hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExtJonathan Cameron2023-11-071-1/+1
* hw/pci-bridge/cxl-upstream: Add serial number extended capability supportJonathan Cameron2023-10-041-2/+13
* hw/pci-bridge/cxl_upstream: Fix bandwidth entry base unit for SSLBISDave Jiang2023-09-211-1/+1
* hw/pci-bridge/cxl_upstream.c: Use g_new0() in build_cdat_table()Peter Maydell2023-08-031-4/+1
* hw/cxl: cdat: Fix failure to free buffer in erorr pathsJonathan Cameron2023-05-191-0/+3
* pci: drop redundant PCIDeviceClass::is_bridge fieldIgor Mammedov2022-12-211-1/+0
* hw/pci-bridge/cxl-upstream: Add a CDAT table access DOEJonathan Cameron2022-11-071-1/+194
* pci-bridge/cxl_upstream: Add a CXL switch upstream portJonathan Cameron2022-06-161-0/+216