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* hw/pci-host/aspeed: Disable Root Device and place Root Port at 00:00.0 to ↵Jamin Lin2025-09-291-0/+2
| | | | | | | | | | | | AST2700 AST2700 does not implement a PCIe Root Device; each RC exposes a single PCIe Root Port at devfn 0:0.0. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-12-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* hw/pci-host/aspeed: Add AST2700 PCIe config with dedicated H2X blocksJamin Lin2025-09-291-0/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce PCIe config (H2X) support for the AST2700 SoC. Unlike the AST2600, the AST2700 provides three independent Root Complexes, each with its own H2X (AHB to PCIe bridge) register block of size 0x100. All RCs use the same MSI address (0x000000F0). The H2X block includes two different access paths: 1. CFGI (internal bridge): used to access the host bridge itself, always with BDF=0. The AST2700 controller simplifies the design by exposing only one register (H2X_CFGI_TLP) with fields for ADDR[15:0], BEN[19:16], and WR[20]. This is not a full TLP descriptor as in the external case. For QEMU readability and code reuse, the model converts H2X_CFGI_TLP into a standard TLP TX descriptor with BDF forced to 0 and then calls the existing helpers aspeed_pcie_cfg_readwrite() and aspeed_pcie_cfg_translate_write(). 2. CFGE (external EP access): used to access external endpoints. The AST2700 design provides H2X_CFGE_TLP1 and a small FIFO at H2X_CFGE_TLPN. For reads, TX DESC0 is stored in TLP1 and DESC1/DESC2 in TLPN FIFO slots. For writes, TX DESC0 is stored in TLP1, DESC1/DESC2 in TLPN FIFO[0..1], and TX write data in TLPN FIFO[2]. The implementation extends AspeedPCIECfgState with a small FIFO and index, wires up new register definitions for AST2700, and adds a specific ops table and class (TYPE_ASPEED_2700_PCIE_CFG). The reset handler clears the FIFO state. Interrupt and MSI status registers are also supported. This provides enough modeling for firmware and drivers to use any of the three PCIe RCs on AST2700 with their own dedicated H2X config window, while reusing existing TLP decode helpers in QEMU. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-11-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* hw/pci-host/aspeed: Add AST2700 PCIe PHYJamin Lin2025-09-291-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a PCIe Host Controller PHY model for AST2700. This adds an AST2700 specific PHY type (TYPE_ASPEED_2700_PCIE_PHY) with a 0x800 byte register space and link-status bits compatible with the firmware’s expectations. AST2700 provides three PCIe RCs; PCIe0 and PCIe1 are GEN4, PCIe2 is GEN2. The PHY exposes: PEHR_2700_LINK_GEN2 at 0x344, bit 18 indicates GEN2 link up PEHR_2700_LINK_GEN4 at 0x358, bit 8 indicates GEN4 link up In real hardware these GEN2/GEN4 link bits are mutually exclusive. QEMU does not model GEN2 vs GEN4 signaling differences, so the reset handler sets both bits to 1. This keeps the model simple and lets firmware see the link as up; firmware will read the appropriate register per RC port to infer the intended mode. The header gains TYPE_ASPEED_2700_PCIE_PHY; the new class derives from TYPE_ASPEED_PCIE_PHY, sets nr_regs to 0x800 >> 2, and installs an AST2700 reset routine that programs the class code (0x06040011) and the GEN2/GEN4 status bits. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-10-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* hw/pci-host/aspeed: Add MSI support and per-RC IOMMU address spaceJamin Lin2025-09-292-0/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add MSI support to the ASPEED PCIe RC/Config model and introduce a per-RC "IOMMU root" address space to correctly route MSI writes. On AST2700 all RCs use the same MSI address, and the MSI target is PCI system memory (not normal DRAM). If the MSI window were mapped into real system RAM, an endpoint's write could be observed by other RCs and spuriously trigger their interrupts. To avoid this, each RC now owns an isolated IOMMU root AddressSpace that contains a small MSI window and a DRAM alias region for normal DMA. The MSI window captures writes and asserts the RC IRQ. MSI status bits are tracked in new H2X RC_H registers (R_H2X_RC_H_MSI_EN{0,1} and R_H2X_RC_H_MSI_STS{0,1}). Clearing all status bits drops the IRQ. The default MSI address is set to 0x1e77005c and can be overridden via the msi-addr property. This keeps MSI traffic contained within each RC while preserving normal DMA to system DRAM. It enables correct MSI/MSI-X interrupt delivery when multiple RCs use the same MSI target address. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-7-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* hw/pci-host/aspeed: Add AST2600 PCIe Root Port and make address configurableJamin Lin2025-09-291-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce an ASPEED PCIe Root Port and wire it under the RC. The root port is modeled as TYPE_ASPEED_PCIE_ROOT_PORT (subclass of TYPE_PCIE_ROOT_PORT). Key changes: - Add TYPE_ASPEED_PCIE_ROOT_PORT (PCIESlot-based) with vendor/device IDs and AER capability offset. - Extend AspeedPCIERcState to embed a root_port instance and a configurable rp_addr. - Add "rp-addr" property to the RC to place the root port at a specific devfn on the root bus. - Set the root port's "chassis" property to ensure a unique chassis per RC. - Extend AspeedPCIECfgClass with rc_rp_addr defaulting to PCI_DEVFN(8,0). Rationale: - AST2600 places the root port at 80:08.0 (bus 0x80, dev 8, fn 0). - AST2700 must place the root port at 00:00.0, and it supports three RCs. Each root port must therefore be uniquely identifiable; uses the PCIe "chassis" ID for that. - Providing a configurable "rp-addr" lets platforms select the correct devfn per SoC family, while the "chassis" property ensures uniqueness across multiple RC instances on AST2700. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-6-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* hw/pci-host/aspeed: Add AST2600 PCIe Root Device supportJamin Lin2025-09-291-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | Introduce a PCIe Root Device for AST2600 platform. The AST2600 root complex exposes a PCIe root device at bus 80, devfn 0. This root device is implemented as a child of the PCIe RC and modeled as a host bridge PCI function (class_id = PCI_CLASS_BRIDGE_HOST). Key changes: - Add a new device type "aspeed.pcie-root-device". - Instantiate the root device as part of AspeedPCIERcState. - Initialize it during RC realize() and attach it to the root bus. - Mark the root device as non-user-creatable. - Add RC boolean property "has-rd" to control whether the Root Device is created (platforms can enable/disable it as needed). Note: Only AST2600 implements this PCIe root device. AST2700 does not provide one. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-5-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* hw/pci-host/aspeed: Add AST2600 PCIe config space and host bridgeJamin Lin2025-09-292-0/+425
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce PCIe config and host bridge model for the AST2600 platform. This patch adds support for the H2X (AHB to PCIe Bus Bridge) controller with a 0x100 byte register space. The register layout is shared between two root complexes: 0x00–0x7f is common, 0x80–0xbf for RC_L, and 0xc0–0xff for RC_H. Only RC_H is modeled in this implementation. The RC_H bus uses bus numbers in the 0x80–0xff range instead of the standard root bus 0x00. To allow the PCI subsystem to discover devices, the host bridge logic remaps the root bus number back to 0x00 whenever the configured bus number matches the "bus-nr" property. New MMIO callbacks are added for the H2X config space: - aspeed_pcie_cfg_read() and aspeed_pcie_cfg_write() handle register accesses. - aspeed_pcie_cfg_readwrite() provides configuration read/write support. - aspeed_pcie_cfg_translate_write() handles PCIe byte-enable semantics for write operations. The reset handler initializes the H2X register block with default values as defined in the AST2600 datasheet. Additional changes: - Implement ASPEED PCIe root complex (TYPE_ASPEED_PCIE_RC). - Wire up interrupt propagation via aspeed_pcie_rc_set_irq(). - Add tracepoints for config read/write and INTx handling. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-4-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* hw/pci-host/aspeed: Add AST2600 PCIe PHY modelJamin Lin2025-09-294-0/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces an initial ASPEED PCIe PHY/host controller model to support the AST2600 SoC. It provides a simple register block with MMIO read/write callbacks, integration into the build system, and trace events for debugging. Key changes: 1. PCIe PHY MMIO read/write callbacks Implemented aspeed_pcie_phy_read() and aspeed_pcie_phy_write() to handle 32-bit register accesses. 2. Build system and Kconfig integration Added CONFIG_PCI_EXPRESS_ASPEED in hw/pci-host/Kconfig and meson rules. Updated ASPEED_SOC in hw/arm/Kconfig to imply PCI_DEVICES and select PCI_EXPRESS_ASPEED. 3. Trace events for debug New tracepoints aspeed_pcie_phy_read and aspeed_pcie_phy_write allow monitoring MMIO accesses. 4. Register space and defaults (AST2600 reference) Expose a 0x100 register space, as documented in the AST2600 datasheet. On reset, set default values: PEHR_ID: Vendor ID = ASPEED, Device ID = 0x1150 PEHR_CLASS_CODE = 0x06040006 PEHR_DATALINK = 0xD7040022 PEHR_LINK: bit[5] set to 1 to indicate link up. This provides a skeleton device for the AST2600 platform. It enables firmware to detect the PCIe link as up by default and allows future extension. This commit is the starting point of the series to introduce ASPEED PCIe Root Complex (RC) support. Based on previous work from Cédric Le Goater, the following commits in this series extend and refine the implementation: - Add a PCIe Root Port so that devices can be attached without requiring an extra bridge. - Restrict the Root Port device instantiation to the AST2600 platform. - Integrate aspeed_cfg_translate_write() to support both AST2600 and AST2700. - Add MSI support and a preliminary RC IOMMU address space. - Fix issues with MSI interrupt clearing. - Extend support to the AST2700 SoC. - Drop the AST2600 RC_L support. - Introduce PCIe RC functional tests covering both AST2600 and AST2700. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250919093017.338309-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* hw/pci-host/astro: Don't call pci_regsiter_root_bus() in initPeter Maydell2025-09-231-13/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the astro PCI host bridge device, we call pci_register_root_bus() in the device's instance_init. This is a problem for two reasons * the PCI bridge is then available to the rest of the simulation (e.g. via pci_qdev_find_device()), even though it hasn't yet been realized * we do not attempt to unregister in an instance_deinit, which means that if you go through an instance_init -> deinit lifecycle the freed memory for the host-bridge device is left on the pci_host_bridges list ASAN reports the resulting use-after-free: ==1776584==ERROR: AddressSanitizer: heap-use-after-free on address 0x51f00000cb00 at pc 0x5b2d460a89b5 bp 0x7ffef7617f50 sp 0x7ffef7617f48 WRITE of size 8 at 0x51f00000cb00 thread T0 #0 0x5b2d460a89b4 in pci_host_bus_register /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../hw/pci/pci.c:608:5 #1 0x5b2d46093566 in pci_root_bus_internal_init /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../hw/pci/pci.c:677:5 #2 0x5b2d460935e0 in pci_root_bus_new /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../hw/pci/pci.c:706:5 #3 0x5b2d46093fe5 in pci_register_root_bus /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../hw/pci/pci.c:751:11 #4 0x5b2d46fe2335 in elroy_pcihost_init /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../hw/pci-host/astro.c:455:16 0x51f00000cb00 is located 1664 bytes inside of 3456-byte region [0x51f00000c480,0x51f00000d200) freed by thread T0 here: #0 0x5b2d4582385a in free (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/qemu-system-hppa+0x17ad85a) (BuildId: 692b49eedc6fb0ef618bbb6784a09311b3b7f1e8) #1 0x5b2d47160723 in object_finalize /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../qom/object.c:734:9 #2 0x5b2d471589db in object_unref /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../qom/object.c:1232:9 #3 0x5b2d477d373c in qmp_device_list_properties /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../qom/qom-qmp-cmds.c:237:5 previously allocated by thread T0 here: #0 0x5b2d45823af3 in malloc (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/qemu-system-hppa+0x17adaf3) (BuildId: 692b49eedc6fb0ef618bbb6784a09311b3b7f1e8) #1 0x79728fa08b09 in g_malloc (/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x62b09) (BuildId: 1eb6131419edb83b2178b682829a6913cf682d75) #2 0x5b2d471595fc in object_new_with_type /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../qom/object.c:767:15 #3 0x5b2d47159409 in object_new_with_class /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../qom/object.c:782:12 #4 0x5b2d477d29a5 in qmp_device_list_properties /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../qom/qom-qmp-cmds.c:206:11 Cc: qemu-stable@nongnu.org Fixes: e029bb00a79be ("hw/pci-host: Add Astro system bus adapter found on PA-RISC machines") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3118 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250918114259.1802337-3-peter.maydell@linaro.org>
* hw/pci-host/dino: Don't call pci_register_root_bus() in initPeter Maydell2025-09-231-41/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the dino PCI host bridge device, we call pci_register_root_bus() in the device's instance_init. This is a problem for two reasons * the PCI bridge is then available to the rest of the simulation (e.g. via pci_qdev_find_device()), even though it hasn't yet been realized * we do not attempt to unregister in an instance_deinit, which means that if you go through an instance_init -> deinit lifecycle the freed memory for the host-bridge device is left on the pci_host_bridges list ASAN reports the resulting use-after-free: ==1771223==ERROR: AddressSanitizer: heap-use-after-free on address 0x527000018f80 at pc 0x5b4b9d3369b5 bp 0x7ffd01929980 sp 0x7ffd01929978 WRITE of size 8 at 0x527000018f80 thread T0 #0 0x5b4b9d3369b4 in pci_host_bus_register /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../hw/pci/pci.c:608:5 #1 0x5b4b9d321566 in pci_root_bus_internal_init /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../hw/pci/pci.c:677:5 #2 0x5b4b9d3215e0 in pci_root_bus_new /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../hw/pci/pci.c:706:5 #3 0x5b4b9d321fe5 in pci_register_root_bus /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../hw/pci/pci.c:751:11 #4 0x5b4b9d390521 in dino_pcihost_init /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../hw/pci-host/dino.c:473:16 0x527000018f80 is located 1664 bytes inside of 12384-byte region [0x527000018900,0x52700001b960) freed by thread T0 here: #0 0x5b4b9cab185a in free (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/qemu-system-hppa+0x17ad85a) (BuildId: ca496bb2e4fc750ebd289b448bad8d99c0ecd140) #1 0x5b4b9e3ee723 in object_finalize /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../qom/object.c:734:9 #2 0x5b4b9e3e69db in object_unref /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../qom/object.c:1232:9 #3 0x5b4b9ea6173c in qmp_device_list_properties /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../qom/qom-qmp-cmds.c:237:5 #4 0x5b4b9ec4e0f3 in qmp_marshal_device_list_properties /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/qapi/qapi-commands-qdev.c:65:14 previously allocated by thread T0 here: #0 0x5b4b9cab1af3 in malloc (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/qemu-system-hppa+0x17adaf3) (BuildId: ca496bb2e4fc750ebd289b448bad8d99c0ecd140) #1 0x799d8270eb09 in g_malloc (/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x62b09) (BuildId: 1eb6131419edb83b2178b682829a6913cf682d75) #2 0x5b4b9e3e75fc in object_new_with_type /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../qom/object.c:767:15 #3 0x5b4b9e3e7409 in object_new_with_class /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../qom/object.c:782:12 #4 0x5b4b9ea609a5 in qmp_device_list_properties /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/hppa-asan/../../qom/qom-qmp-cmds.c:206:11 where we allocated one instance of the dino device, put it on the list, freed it, and then trying to allocate a second instance touches the freed memory on the pci_host_bridges list. Fix this by deferring all the setup of memory regions and registering the PCI bridge to the device's realize method. This brings it into line with almost all other PCI host bridges, which call pci_register_root_bus() in realize. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3118 Fixes: 63901b6cc4d8b4 ("dino: move PCI bus initialisation to dino_pcihost_init()") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250918114259.1802337-2-peter.maydell@linaro.org>
* hw/pci-host/gpex-acpi: Use build_pci_host_bridge_osc_methodEric Auger2025-07-152-57/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gpex build_host_bridge_osc() and x86 originated build_pci_host_bridge_osc_method() are mostly identical. In GPEX, SUPP is set to CDW2 but is not further used. CTRL is same as Local0. So let gpex code reuse build_pci_host_bridge_osc_method() and remove build_host_bridge_osc(). Also add an imply ACPI_PCI clause along with PCI_EXPRESS_GENERIC_BRIDGE to compile hw/acpi/pci.c when its dependency is resolved (ie. CONFIG_ACPI_PCI). This is requested to link qemu-system-mips64el. The disassembled DSDT difference is given below: * Original Table Header: * Signature "DSDT" - * Length 0x00001A4F (6735) + * Length 0x00001A35 (6709) * Revision 0x02 - * Checksum 0xBF + * Checksum 0xDD * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) @@ -1849,27 +1849,26 @@ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001) { CreateDWordField (Arg3, 0x04, CDW2) CreateDWordField (Arg3, 0x08, CDW3) - SUPP = CDW2 /* \_SB_.PCI0._OSC.CDW2 */ - CTRL = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ - CTRL &= 0x1F + Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + Local0 &= 0x1F If ((Arg1 != One)) { CDW1 |= 0x08 } - If ((CDW3 != CTRL)) + If ((CDW3 != Local0)) { CDW1 |= 0x10 } - CDW3 = CTRL /* \_SB_.PCI0.CTRL */ - Return (Arg3) + CDW3 = Local0 } Else { CDW1 |= 0x04 - Return (Arg3) } + + Return (Arg3) } Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Message-Id: <20250714080639.2525563-10-eric.auger@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* hw/pci-host/gpex-acpi: Use GED acpi pcihp propertyEric Auger2025-07-151-1/+2
| | | | | | | | | | | | Retrieve the acpi pcihp property value from the ged. In case this latter is not set, PCI native hotplug is used on pci0. For expander bridges we keep pci native hotplug, as done on x86 q35. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Message-Id: <20250714080639.2525563-8-eric.auger@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* hw/pci-host/gpex-acpi: Split host bridge OSC and DSM generationEric Auger2025-07-151-11/+21
| | | | | | | | | | | | | | | | | | | | | | | acpi_dsdt_add_pci_osc() name is confusing as it gives the impression it appends the _OSC method but in fact it also appends the _DSM method for the host bridge. Let's split the function into two separate ones and let them return the method Aml pointer instead. This matches the way it is done on x86 (build_q35_osc_method). In a subsequent patch we will replace the gpex method by the q35 implementation that will become shared between ARM and x86. acpi_dsdt_add_host_bridge_methods is a new top helper that generates both the _OSC and _DSM methods. We take the opportunity to move SUPP and CTRL in the _osc method that use them. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20250714080639.2525563-6-eric.auger@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* hw/pci-host/gpex-acpi: Add native_pci_hotplug arg to acpi_dsdt_add_pci_oscEric Auger2025-07-151-7/+8
| | | | | | | | | | | | | Add a new argument to acpi_dsdt_add_pci_osc to be able to disable native pci hotplug. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Message-Id: <20250714080639.2525563-4-eric.auger@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* qemu: Declare all load/store helper in 'qemu/bswap.h'Philippe Mathieu-Daudé2025-07-155-2/+3
| | | | | | | | | | | | Restrict "exec/tswap.h" to the tswap*() methods, move the load/store helpers with the other ones declared in "qemu/bswap.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20250708215320.70426-8-philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* hw/ppc/e500: Use SysBusDevice API to access TYPE_CCSR's internal resourcesBernhard Beschow2025-06-101-4/+4
| | | | | | | | | | | | | | | Rather than accessing the attributes of TYPE_CCSR directly, use the SysBusDevice API which exists exactly for that purpose. Furthermore, registering the memory region with the SysBusDevice API makes it show up in QMP's `info qom-tree` command. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> [balaton: rebased] Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <619a58d1f83d2aad5b4feec930d46c64abff0977.1748012109.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* hw/pci-host/raven: Revert "raven: Move BIOS loading from board code to PCI host"BALATON Zoltan2025-06-101-55/+0
| | | | | | | | | | | | | | | This reverts commit d0b25425749d5525b2ba6d9d966d8800a5643b35. Loading firmware from the PCI host is unusual and raven is only used by one board so this does not simplify anything but rather complicates it. Revert to loading firmware from board code as that is the usual way and also because raven has nothing to do with ROM so it is not a good place for this. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <4ca4f71bf661923d9a91b7e6776a0e40726e2337.1746374076.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* hw/pci-host/raven: Remove is-legacy-prep propertyBALATON Zoltan2025-06-101-20/+12
| | | | | | | | | | | This was a workaround for the prep machine that was removed 5 years ago so this is no longer needed. Fixes: b2ce76a073 (hw/ppc/prep: Remove the deprecated "prep" machine and the OpenHackware BIOS) Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <0d41c18a8831bd4c8b0948eda3ef8f60f5a311f3.1746374076.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* hw/pci-host/gt64120: Fix endianness handlingRakesh Jeyasingh2025-05-201-34/+48
| | | | | | | | | | | | | | | | | | | | | | | | The GT-64120 PCI controller requires special handling where: 1. Host bridge(bus 0 ,device 0) must never be byte-swapped 2. Other devices follow MByteSwap bit in GT_PCI0_CMD The previous implementation incorrectly swapped all accesses, breaking host bridge detection (lspci -d 11ab:4620). Changes made: 1. Removed gt64120_update_pci_cfgdata_mapping() and moved data_mem initialization to gt64120_realize() for cleaner setup 2. Implemented custom read/write handlers that: - Preserve host bridge accesses (extract32(config_reg,11,13)==0) - apply swapping only for non-bridge devices in big-endian mode Fixes: 145e2198 ("hw/mips/gt64xxx_pci: Endian-swap using PCI_HOST_BRIDGE MemoryRegionOps") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2826 Signed-off-by: Rakesh Jeyasingh <rakeshjb010@gmail.com> Tested-by: Thomas Huth <thuth@redhat.com> Link: https://lore.kernel.org/r/20250429170354.150581-2-rakeshjb010@gmail.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into stagingStefan Hajnoczi2025-05-121-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | trivial patches for 2025-05-09 # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEZKoqtTHVaQM2a/75gqpKJDselHgFAmgeawQACgkQgqpKJDse # lHgRcg/+LmwJJvMViRD/OJFRqp60zBnPyuXFyJJQ3q7lBsE5Vr8xdZUkrGUrQ0p+ # ef6KRnqesaYFH6lEZIJIYXLPalHDIJg6NCHnOphXYoexYQ61e8Y07lmTJlCXK+T8 # rTf230ZC0Jzuy6BM5cmk7cMnNtVp8gPgK5SOK4u5OJSQTBMDb/XZZkLdnjj5ChGJ # aX4qZ9fDLOWJoteXA4QWx6F8K1ONvooS5IMYB6AFJI2xMASq8nVETPXIuSComBDY # 2+krw8hLu6PoPd9yWjlnsE8y4NvNWyRAc2CVm3SI30PEIchvDiQuVJpUD5Q3xZy5 # 2OLD9nv9PqezERbD2ZdSa08VlbEeoyrRinBtZJv7m9qkiU8B4TGDn7hx23MAu6Zx # POF+P1Bc4kixL46pDMll5ETcRr6k184anTvpPWhOynJZBZusc4rX3UHSrVJMsfTx # DPjToUwRw50prtHyuYWWyoxZ+i9BOHAgiT/zOor2tte3xT/mvc8my9m2+YgDHnqE # u8wTnH3zYqexOwLctC3aslSbR1sqqrCsKOA8ZXQ33Ac6kV1q2T4Om4stmRbewjMG # ROsNky2iiKbPsSJsmZHVuv0vy3sHRVWyyp8ClSP5S+gNysEVu/Oka3E0KQ/vg72y # lDA3kNKS2t7ZSPXoLFaSWI6aOnSpKZgNW09wSVDh/AjKV+LbC6c= # =EoxT # -----END PGP SIGNATURE----- # gpg: Signature made Fri 09 May 2025 16:52:20 EDT # gpg: using RSA key 64AA2AB531D56903366BFEF982AA4A243B1E9478 # gpg: Good signature from "Michael Tokarev <mjt@debian.org>" [unknown] # gpg: aka "Michael Tokarev <mjt@corpit.ru>" [unknown] # gpg: aka "Michael Tokarev <mjt@tls.msk.ru>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 9D8B E14E 3F2A 9DD7 9199 28F1 61AD 3D98 ECDF 2C8E # Subkey fingerprint: 64AA 2AB5 31D5 6903 366B FEF9 82AA 4A24 3B1E 9478 * tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu: (21 commits) docs/devel/testing/functional: Fix typo docs: replace `-hda` with `-drive` & update `root=` kernel parameter qapi/machine-target.json: fix "in in" typo in comment hw/display/apple-gfx.m: fix "in in" typo in comment qapi/qom.json: fix "the the" typo in comment include/hw/xen/interface/io/blkif.h: fix "the the" typo in comment include/exec/cpu-common.h: fix "the the" typo in comment hw/xen/xen-hvm-common.c: fix "the the" typo in comment block.c: fix "the the" typo in comment linux-user/mmap.c: fix "of of" typo in comment hw/acpi/pcihp: Fix typo in function name hw/pci-host/gpex-acpi: Fix typo in comment hw/net/e1000: Remove stray empty comment in header qom/object: Fix typo in comment hw/core/machine: Fix indentation hw/i386/acpi-build: Fix typo in function name hw/acpi/ich9: Remove ICH9_DEBUG macro hw/i386/acpi-build: Update document reference hw/i386/acpi-build: Fix typo and grammar in comment hw/isa/ich9: Remove stray empty comment ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * hw/pci-host/gpex-acpi: Fix typo in commentGustavo Romero2025-05-091-1/+1
| | | | | | | | | | | | | | | | | | Fix typo in a comment about the creation of the ACPI CRS method. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* | hw/pci-host/designware: Fix viewport configurationBernhard Beschow2025-05-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit 6970f91ac781, "hw/pci-host/designware: Use deposit/extract API" accidentally introduced a copy-and-paste error, causing Linux 6.14 to hang when initializing the PCIe bridge on the imx8mp-evk machine. This fix corrects the error. Fixes: 6970f91ac781 ("hw/pci-host/designware: Use deposit/extract API") Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250501183445.2389-3-shentey@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/pci-host/designware: Remove unused includeBernhard Beschow2025-05-061-1/+0
|/ | | | | | | | | | The DEFINE_TYPES() macro doesn't need the qemu/module.h include. Fixes: 13a07eb146c8 ("hw/pci-host/designware: Declare CPU QOM types using DEFINE_TYPES() macro") Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250501183445.2389-2-shentey@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* qom: Make InterfaceInfo[] uses constPhilippe Mathieu-Daudé2025-04-2520-25/+25
| | | | | | | | | | | Mechanical change using: $ sed -i -E 's/\(InterfaceInfo.?\[/\(const InterfaceInfo\[/g' \ $(git grep -lE '\(InterfaceInfo.?\[\]\)') Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250424194905.82506-7-philmd@linaro.org>
* qom: Have class_init() take a const data argumentPhilippe Mathieu-Daudé2025-04-2529-64/+69
| | | | | | | | | | Mechanical change using gsed, then style manually adapted to pass checkpatch.pl script. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250424194905.82506-4-philmd@linaro.org>
* hw/pci-host/designware: Use deposit/extract APIPhilippe Mathieu-Daudé2025-04-251-31/+17
| | | | | | | | | Prefer the safer (less bug-prone) deposit/extract API to access lower/upper 32-bit of 64-bit registers. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org> Message-Id: <20250331152041.74533-3-philmd@linaro.org>
* exec/cpu-all: remove exec/target_page includePierrick Bouvier2025-04-231-0/+1
| | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* include/system: Move exec/address-spaces.h to system/address-spaces.hRichard Henderson2025-04-231-1/+1
| | | | | | | | Convert the existing includes with sed. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* include/system: Move exec/memory.h to system/memory.hRichard Henderson2025-04-231-1/+1
| | | | | | | | | | | | Convert the existing includes with sed -i ,exec/memory.h,system/memory.h,g Move the include within cpu-all.h into a !CONFIG_USER_ONLY block. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* hw/pci-host/designware: Fix ATU_UPPER_TARGET register accessPhilippe Mathieu-Daudé2025-03-311-1/+1
| | | | | | | | | | | | | Fix copy/paste error writing to the ATU_UPPER_TARGET register, we want to update the upper 32 bits. Cc: qemu-stable@nongnu.org Reported-by: Joey <jeundery@gmail.com> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2861 Fixes: d64e5eabc4c ("pci: Add support for Designware IP block") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org> Message-Id: <20250331152041.74533-2-philmd@linaro.org>
* ppc/pnv/phb4: Add pervasive chiplet support to PHB4/5Nicholas Piggin2025-03-111-1/+54
| | | | | | | | | | | | | | | | | | Each non-core chiplet on a chip has a "pervasive chiplet" unit and its xscom register set. This adds support for PHB4/5. skiboot reads the CPLT_CONF1 register in __phb4/5_get_max_link_width(), which shows up as unimplemented xscom reads. Set a value in PCI CONF1 register's link-width field to demonstrate skiboot doing something interesting with it. In the bigger picture, it might be better to model the pervasive chiplet type as parent that each non-core chiplet model derives from. For now this is enough to get the PHB registers implemented and working for skiboot, and provides a second example (after the N1 chiplet) that will help if the design is reworked as such. Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
* hw/arm/fsl-imx8mp: Add PCIe supportBernhard Beschow2025-02-253-0/+102
| | | | | | | | | | Linux checks for the PLLs in the PHY to be locked, so implement a model emulating that. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-9-shentey@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/pci-host/designware: Prevent device attachment on internal PCIe root busBernhard Beschow2025-02-251-1/+17
| | | | | | | | | | | | | | | | | On the real device, the PCIe root bus is only connected to a PCIe bridge and does not allow for direct attachment of devices. Doing so in QEMU results in no PCI devices being detected by Linux. Instead, PCI devices should plug into the secondary PCIe bus spawned by the internal PCIe bridge. Unfortunately, QEMU defaults to plugging devices into the PCIe root bus. To work around this, every PCI device created on the command line needs an extra `bus=dw-pcie` option which is error prone. Fix that by marking the PCIe root bus as full which makes QEMU decend into the child PCIe bus. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-3-shentey@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/pci-host: Mark versatile regions as little-endianPhilippe Mathieu-Daudé2025-02-161-2/+2
| | | | | | | | | | | | This device is only used by the ARM targets, which are only built as little-endian. Therefore the DEVICE_NATIVE_ENDIAN definition expand to DEVICE_LITTLE_ENDIAN (besides, the DEVICE_BIG_ENDIAN case isn't tested). Simplify directly using DEVICE_LITTLE_ENDIAN. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250212113938.38692-5-philmd@linaro.org>
* hw/pci-host/astro: Add LMMIO range supportHelge Deller2025-02-041-0/+52
| | | | | | | | | | | | | Each Astro on 64-bit machines supports up to four LMMIO regions. Those regions are used by graphic cards and other PCI devices which need to map huge memory areas. The LMMIO regions are configured and set up by SeaBIOS-hppa and then used as-is by the operating systems (Linux, HP-UX). With this addition it's now possible to add other PCI graphic cards on the command line, e.g. with "-device ati-vga". Signed-off-by: Helge Deller <deller@gmx.de>
* hw/loader: Pass ELFDATA endian order argument to load_elf()Philippe Mathieu-Daudé2025-01-311-2/+2
| | | | | | | | | | | | | | | | | Rather than passing a boolean 'is_big_endian' argument, directly pass the ELFDATA, which can be unspecified using the ELFDATANONE value. Update the call sites: 0 -> ELFDATA2LSB 1 -> ELFDATA2MSB TARGET_BIG_ENDIAN -> TARGET_BIG_ENDIAN ? ELFDATA2MSB : ELFDATA2LSB Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250127113824.50177-7-philmd@linaro.org>
* hw/pci-host/designware: Expose MSI IRQBernhard Beschow2025-01-271-4/+3
| | | | | | | | | | Fixes INTD and MSI interrupts poking the same IRQ line without keeping track of each other's IRQ level. Furthermore, SoCs such as the i.MX 8M Plus don't share the MSI IRQ with the INTx lines, so expose it as a dedicated pin. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/pci-host/gpex: Allow more than 4 legacy IRQsAlexander Graf2024-12-301-9/+34
| | | | | | | | | | | | | | | | Some boards such as vmapple don't do real legacy PCI IRQ swizzling. Instead, they just keep allocating more board IRQ lines for each new legacy IRQ. Let's support that mode by giving instantiators a new "nr_irqs" property they can use to support more than 4 legacy IRQ lines. In this mode, GPEX will export more IRQ lines, one for each device. Signed-off-by: Alexander Graf <graf@amazon.com> Signed-off-by: Phil Dennis-Jordan <phil@philjordan.eu> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20241223221645.29911-9-phil@philjordan.eu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* Merge tag 'exec-20241220' of https://github.com/philmd/qemu into stagingStefan Hajnoczi2024-12-218-9/+9
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Accel & Exec patch queue - Ignore writes to CNTP_CTL_EL0 on HVF ARM (Alexander) - Add '-d invalid_mem' logging option (Zoltan) - Create QOM containers explicitly (Peter) - Rename sysemu/ -> system/ (Philippe) - Re-orderning of include/exec/ headers (Philippe) Move a lot of declarations from these legacy mixed bag headers: . "exec/cpu-all.h" . "exec/cpu-common.h" . "exec/cpu-defs.h" . "exec/exec-all.h" . "exec/translate-all" to these more specific ones: . "exec/page-protection.h" . "exec/translation-block.h" . "user/cpu_loop.h" . "user/guest-host.h" . "user/page-protection.h" # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmdlnyAACgkQ4+MsLN6t # wN6mBw//QFWi7CrU+bb8KMM53kOU9C507tjn99LLGFb5or73/umDsw6eo/b8DHBt # KIwGLgATel42oojKfNKavtAzLK5rOrywpboPDpa3SNeF1onW+99NGJ52LQUqIX6K # A6bS0fPdGG9ZzEuPpbjDXlp++0yhDcdSgZsS42fEsT7Dyj5gzJYlqpqhiXGqpsn8 # 4Y0UMxSL21K3HEexlzw2hsoOBFA3tUm2ujNDhNkt8QASr85yQVLCypABJnuoe/// # 5Ojl5wTBeDwhANET0rhwHK8eIYaNboiM9fHopJYhvyw1bz6yAu9jQwzF/MrL3s/r # xa4OBHBy5mq2hQV9Shcl3UfCQdk/vDaYaWpgzJGX8stgMGYfnfej1SIl8haJIfcl # VMX8/jEFdYbjhO4AeGRYcBzWjEJymkDJZoiSWp2NuEDi6jqIW+7yW1q0Rnlg9lay # ShAqLK5Pv4zUw3t0Jy3qv9KSW8sbs6PQxtzXjk8p97rTf76BJ2pF8sv1tVzmsidP # 9L92Hv5O34IqzBu2oATOUZYJk89YGmTIUSLkpT7asJZpBLwNM2qLp5jO00WVU0Sd # +kAn324guYPkko/TVnjC/AY7CMu55EOtD9NU35k3mUAnxXT9oDUeL4NlYtfgrJx6 # x1Nzr2FkS68+wlPAFKNSSU5lTjsjNaFM0bIJ4LCNtenJVP+SnRo= # =cjz8 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 20 Dec 2024 11:45:20 EST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'exec-20241220' of https://github.com/philmd/qemu: (59 commits) util/qemu-timer: fix indentation meson: Do not define CONFIG_DEVICES on user emulation system/accel-ops: Remove unnecessary 'exec/cpu-common.h' header system/numa: Remove unnecessary 'exec/cpu-common.h' header hw/xen: Remove unnecessary 'exec/cpu-common.h' header target/mips: Drop left-over comment about Jazz machine target/mips: Remove tswap() calls in semihosting uhi_fstat_cb() target/xtensa: Remove tswap() calls in semihosting simcall() helper accel/tcg: Un-inline translator_is_same_page() accel/tcg: Include missing 'exec/translation-block.h' header accel/tcg: Move tcg_cflags_has/set() to 'exec/translation-block.h' accel/tcg: Restrict curr_cflags() declaration to 'internal-common.h' qemu/coroutine: Include missing 'qemu/atomic.h' header exec/translation-block: Include missing 'qemu/atomic.h' header accel/tcg: Declare cpu_loop_exit_requested() in 'exec/cpu-common.h' exec/cpu-all: Include 'cpu.h' earlier so MMU_USER_IDX is always defined target/sparc: Move sparc_restore_state_to_opc() to cpu.c target/sparc: Uninline cpu_get_tb_cpu_state() target/loongarch: Declare loongarch_cpu_dump_state() locally user: Move various declarations out of 'exec/exec-all.h' ... Conflicts: hw/char/riscv_htif.c hw/intc/riscv_aplic.c target/s390x/cpu.c Apply sysemu header path changes to not in the pull request. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * include: Rename sysemu/ -> system/Philippe Mathieu-Daudé2024-12-207-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Headers in include/sysemu/ are not only related to system *emulation*, they are also used by virtualization. Rename as system/ which is clearer. Files renamed manually then mechanical change using sed tool. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Message-Id: <20241203172445.28576-1-philmd@linaro.org>
| * ppc/e500: Avoid abuse of container_get()Peter Xu2024-12-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | container_get() is going to become strict on not allowing to return a non-container. Switch the e500 user to use object_resolve_path_component() explicitly. Cc: Bharat Bhushan <r65777@freescale.com> Cc: qemu-ppc@nongnu.org Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Peter Xu <peterx@redhat.com> Message-ID: <20241121192202.4155849-6-peterx@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* | include/hw/qdev-properties: Remove DEFINE_PROP_END_OF_LISTRichard Henderson2024-12-1917-21/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that all of the Property arrays are counted, we can remove the terminator object from each array. Update the assertions in device_class_set_props to match. With struct Property being 88 bytes, this was a rather large form of terminator. Saves 30k from qemu-system-aarch64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Link: https://lore.kernel.org/r/20241218134251.4724-21-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | hw/pci-host/astro: Remove empty Property listRichard Henderson2024-12-191-5/+0
|/ | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Link: https://lore.kernel.org/r/20241218134251.4724-6-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* hw/pci-host: Constify all PropertyRichard Henderson2024-12-1517-19/+19
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* hw/ppc/pegasos2: Fix IRQ routing from pci.0BALATON Zoltan2024-11-271-0/+1
| | | | | | | | | | | | | | | The MV64361 has two PCI buses one of which is used for AGP on PegasosII. So far we only emulated the PCI bus on pci.1 but some graphics cards are only recognised by some guests when connected to pci.0 corresponding to the AGP port. So far the interrupts were not routed from pci.0 so this patch fixes that allowing the use of both PCI buses. On real board only INTA and INTB are connected for AGP but to avoid surprises we connect all 4 PCI interrupt lines so pci.0 can be used for all PCI cards as well. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
* Merge tag 'hw-misc-20241105' of https://github.com/philmd/qemu into stagingPeter Maydell2024-11-061-25/+19
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Misc HW patch queue - Deprecate a pair of untested microblaze big-endian machines (Philippe) - Arch-agnostic CPU topology checks at machine level (Zhao) - Cleanups on PPC E500 (Bernhard) - Various conversions to DEFINE_TYPES() macro (Bernhard) - Fix RISC-V _pext_u64() name clashing (Pierrick) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmcqqycACgkQ4+MsLN6t # wN7TfhAAkAjpWxFGptNw28LPpnZY/NTGKyXQrIEHu3XnJsZ28c/KZeCAYUUC6/q7 # tAnBMb5GIn2VTyt+ElORseFtHStThoR8WMrcQSlGvCZei9lRNKCW0pVIEUgLZEtT # u8lChpaVAn8gXb885xlaCBBP4SuFHEpASSfWy0mYDIqZL3oRhr9AQ/KwzHFqenbK # Uva4BCWRVnYju6MhfA/pmVP011SUTdCu/fsBTIJT3Xn7Sp7fRNShIzt+1rbmPnR2 # hhRl5bMKUgDUjX5GxeP0LOj/XdX9svlqL42imNQT5FFUMIR6qbrwj4U841mt0uuI # FcthAoILvA2XUJoTESq0iXUoN4FQLtc01onY6k06EoZAnn8WRZRp2dNdu8fYmHMX # y3pcXBK6wEhBVZ2DcGVf1txmieUc4TZohOridU1Xfckp+XVl6J3LtTKJIE56Eh68 # S9OJW1Sz2Io/8FJFvKStX0bhV0nBUyUXmi5PjV4vurS6Gy1aVodiiq3ls6baX05z # /Y8DJGpPByA+GI2prdwq9oTIhEIU2bJDDz32NkwHM99SE25h+iyh21Ap5Ojkegm7 # 1squIskxX3QLtEMxBCe+XIKzEZ51kzNZxmLXvCFW5YetypNdhyULqH/UDWt7hIDN # BSh2w1g/lSw9n6DtEN3rURYAR/uV7/7IMEP8Td2wvcDX4o95Fkw= # =q0cF # -----END PGP SIGNATURE----- # gpg: Signature made Tue 05 Nov 2024 23:32:55 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'hw-misc-20241105' of https://github.com/philmd/qemu: (29 commits) hw/riscv/iommu: fix build error with clang hw/usb/hcd-ehci-sysbus: Prefer DEFINE_TYPES() macro hw/rtc/ds1338: Prefer DEFINE_TYPES() macro hw/i2c/smbus_eeprom: Prefer DEFINE_TYPES() macro hw/block/pflash_cfi01: Prefer DEFINE_TYPES() macro hw/sd/sdhci: Prefer DEFINE_TYPES() macro hw/ppc/mpc8544_guts: Prefer DEFINE_TYPES() macro hw/gpio/mpc8xxx: Prefer DEFINE_TYPES() macro hw/net/fsl_etsec/etsec: Prefer DEFINE_TYPES() macro hw/net/fsl_etsec/miim: Reuse MII constants hw/pci-host/ppce500: Prefer DEFINE_TYPES() macro hw/pci-host/ppce500: Reuse TYPE_PPC_E500_PCI_BRIDGE define hw/i2c/mpc_i2c: Prefer DEFINE_TYPES() macro hw/i2c/mpc_i2c: Convert DPRINTF to trace events for register access hw/ppc/mpc8544_guts: Populate POR PLL ratio status register hw/ppc/e500: Add missing device tree properties to i2c controller node hw/ppc/e500: Remove unused "irqs" parameter hw/ppc/e500: Prefer QOM cast hw/core: Add a helper to check the cache topology level hw/core: Check smp cache topology support for machine ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/pci-host/ppce500: Prefer DEFINE_TYPES() macroBernhard Beschow2024-11-051-24/+18
| | | | | | | | | | | | | | Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20241103133412.73536-15-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * hw/pci-host/ppce500: Reuse TYPE_PPC_E500_PCI_BRIDGE defineBernhard Beschow2024-11-051-1/+1
| | | | | | | | | | | | | | | | | | Prefer a macro rather than a string literal when instantiaging device models. Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20241103133412.73536-14-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* | hw/pci-host/gpex-acpi: Use acpi_uid property.Jonathan Cameron2024-11-041-1/+4
|/ | | | | | | | | | | | Reduce the direct use of PCI internals inside ACPI table creation. Suggested-by: Igor Mammedov <imammedo@redhat.com> Tested-by: "Huang, Ying" <ying.huang@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20240916171017.1841767-10-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* q35: Remove unused mch_mcfg_baseDr. David Alan Gilbert2024-10-031-10/+0
| | | | | | | | | | | | | | mch_mcfg_base has been unused since it was added by 6f1426ab0f ("ich9: APIs for pc guest info") back in 2013. Remove it. Signed-off-by: Dr. David Alan Gilbert <dave@treblig.org> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>