| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | hw/riscv: Move sifive_plic model to hw/intc | Bin Meng | 2020-09-09 | 1 | -1/+1 |
| * | hw/riscv: Move sifive_clint model to hw/intc | Bin Meng | 2020-09-09 | 1 | -1/+1 |
| * | hw/riscv: clint: Avoid using hard-coded timebase frequency | Bin Meng | 2020-09-09 | 1 | -1/+5 |
| * | hw/riscv: microchip_pfsoc: Hook GPIO controllers | Bin Meng | 2020-09-09 | 1 | -0/+14 |
| * | hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs | Bin Meng | 2020-09-09 | 1 | -0/+39 |
| * | hw/riscv: microchip_pfsoc: Connect a DMA controller | Bin Meng | 2020-09-09 | 1 | -0/+15 |
| * | hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card | Bin Meng | 2020-09-09 | 1 | -0/+23 |
| * | hw/riscv: microchip_pfsoc: Connect 5 MMUARTs | Bin Meng | 2020-09-09 | 1 | -0/+30 |
| * | hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board | Bin Meng | 2020-09-09 | 1 | -0/+312 |