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* hw/riscv/sifive_u: Resolve redundant property accessorsBernhard Beschow2022-05-241-20/+4
| | | | | | | | | | The QOM API already provides accessors for uint32 values, so reuse them. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220301225220.239065-3-shentey@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)Tsukasa OI2022-05-241-2/+2
| | | | | | | | | | | | | | | | | | | If specified CPU configuration is not valid, not just it prints error message, it aborts and generates core dumps (depends on the operating system). This kind of error handling should be used only when a serious runtime error occurs. This commit makes error handling on CPU configuration more generous on sifive_e/u and opentitan machines. It now just prints error message and quits (without coredumps and aborts). This is separate from spike/virt because it involves different type (TYPE_RISCV_HART_ARRAY) on sifive_e/u and opentitan machines. Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <09e61e58a7543da44bdb0e0f5368afc8903b4aa6.1652509778.git.research_trasio@irq.a4lg.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: Don't add empty bootargs to device treeBin Meng2022-04-291-1/+1
| | | | | | | | | | | | | | | | | | Commit 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree") tried to avoid adding *NULL* bootargs to device tree, but unfortunately the changes were entirely useless, due to MachineState::kernel_cmdline can't be NULL at all as the default value is given as an empty string. (see hw/core/machine.c::machine_initfn()). Note the wording of *NULL* bootargs is wrong. It can't be NULL otherwise a segfault had already been observed by dereferencing the NULL pointer. It should be worded as *empty" bootargs. Fixes: 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree") Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220421055629.1177285-2-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: Use error_fatal for SoC realisationAlistair Francis2022-01-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | When realising the SoC use error_fatal instead of error_abort as the process can fail and report useful information to the user. Currently a user can see this: $ ../qemu/bld/qemu-system-riscv64 -M sifive_u -S -monitor stdio -display none -drive if=pflash QEMU 6.1.93 monitor - type 'help' for more information (qemu) Unexpected error in sifive_u_otp_realize() at ../hw/misc/sifive_u_otp.c:229: qemu-system-riscv64: OTP drive size < 16K Aborted (core dumped) Which this patch addresses Reported-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220105213937.1113508-8-alistair.francis@opensource.wdc.com>
* hw: Replace trivial drive_get_next() by drive_get()Markus Armbruster2021-12-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drive_get_next() is basically a bad idea. It returns the "next" block backend of a certain interface type. "Next" means bus=0,unit=N, where subsequent calls count N up from zero, per interface type. This lets you define unit numbers implicitly by execution order. If the order changes, or new calls appear "in the middle", unit numbers change. ABI break. Hard to spot in review. A number of machines connect just one backend with drive_get_next(). Change them to use drive_get() directly. This makes the (zero) unit number explicit in the code. Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Subbaraya Sundeep <sundeep.lkml@gmail.com> Cc: Niek Linnenbank <nieklinnenbank@gmail.com> Cc: Andrew Baumann <Andrew.Baumann@microsoft.com> Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org> Cc: Jean-Christophe Dubois <jcd@tribudubois.net> Cc: Alistair Francis <Alistair.Francis@wdc.com> Cc: Bin Meng <bin.meng@windriver.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Artyom Tarasenko <atar4qemu@gmail.com> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Michael Tokarev <mjt@tls.msk.ru> Cc: Laurent Vivier <laurent@vivier.eu> Cc: qemu-arm@nongnu.org Cc: qemu-riscv@nongnu.org Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20211117163409.3587705-3-armbru@redhat.com>
* hw/sd/ssi-sd: Do not create SD card within controller's realizeMarkus Armbruster2021-12-151-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | ssi_sd_realize() creates an "sd-card" device. This is inappropriate, and marked FIXME. Move it to the boards that create these devices. Prior art: commit eb4f566bbb for device "generic-sdhci", and commit 26c607b86b for device "pl181". The device remains not user-creatable, because its users should (and do) wire up its GPIO chip-select line. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Alistair Francis <Alistair.Francis@wdc.com> Cc: Bin Meng <bin.meng@windriver.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org> Cc: qemu-arm@nongnu.org Cc: qemu-riscv@nongnu.org Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20211117163409.3587705-2-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: sifive_u: Use the PLIC config helper functionAlistair Francis2021-10-281-13/+1
| | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20211022060133.3045020-3-alistair.francis@opensource.wdc.com
* hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_idBin Meng2021-10-221-4/+2
| | | | | | | | | | | | | | | | Using memory_region_init_ram(), which can't possibly handle vhost-user, and can't work as expected with '-numa node,memdev' options. Use MachineState::ram instead of manually initializing RAM memory region, as well as by providing MachineClass::default_ram_id to opt in to memdev scheme. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211020014112.7336-6-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel2021-09-211-3/+6
| | | | | | | | | | | | | The RISC-V ACLINT is more modular and backward compatible with original SiFive CLINT so instead of duplicating the original SiFive CLINT implementation we upgrade the current SiFive CLINT implementation to RISC-V ACLINT implementation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210831110603.338681-3-anup.patel@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel2021-09-211-1/+1
| | | | | | | | | | | We will be upgrading SiFive CLINT implementation into RISC-V ACLINT implementation so let's first rename the sources. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210831110603.338681-2-anup.patel@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* sifive_u: Connect the SiFive PWM deviceAlistair Francis2021-09-211-1/+54
| | | | | | | | Connect the SiFive PWM device and expose it via the device tree. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 22f98648b4e012f78529a56f5ca60b0b27852a4d.1631159656.git.alistair.francis@wdc.com
* hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis2021-09-211-1/+1
| | | | | | | | | | | | Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the external MIP bits. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 0364190bfa935058a845c0fa1ecf650328840ad5.1630301632.git.alistair.francis@wdc.com
* arch_init.h: Don't include arch_init.h unnecessarilyPeter Maydell2021-08-261-1/+0
| | | | | | | | | | | arch_init.h only defines the QEMU_ARCH_* enumeration and the arch_type global. Don't include it in files that don't use those. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210730105947.28215-8-peter.maydell@linaro.org
* hw/riscv: sifive_u: Make sure firmware info is 8-byte alignedBin Meng2021-07-151-2/+3
| | | | | | | | | | | | | | | | | | Currently the firmware dynamic info (fw_dyn) is put right after the reset vector, which is not 8-byte aligned on RV64. OpenSBI fw_dynamic uses ld to read contents from 'struct fw_dynamic_info', which expects fw_dyn to be on the 8-byte boundary, otherwise the misaligned load exception may happen. Fortunately this does not cause any issue on QEMU, as QEMU does support misaligned load. RV32 does not have any issue as it is 4-byte aligned already. Change to make sure it is 8-byte aligned which works for both RV32 and RV64. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210708143319.10441-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: sifive_u: Correct the CLINT timebase frequencyBin Meng2021-07-151-2/+5
| | | | | | | | | | At present the CLINT timebase frequency is set to 10MHz on sifive_u, but on the real hardware the timebase frequency is 1Mhz. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210706102616.1922469-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: Use macros for BIOS image namesBin Meng2021-06-081-4/+2
| | | | | | | | | | The OpenSBI BIOS image names are used by many RISC-V machines. Let's define macros for them. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210430071302.1489082-7-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: Support the official PLIC DT bindingsBin Meng2021-06-081-1/+5
| | | | | | | | | | | | The official DT bindings of PLIC uses "sifive,plic-1.0.0" as the compatible string in the upstream Linux kernel. "riscv,plic0" is now legacy and has to be kept for backward compatibility of legacy systems. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210430071302.1489082-4-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: Support the official CLINT DT bindingsBin Meng2021-06-081-1/+5
| | | | | | | | | | | | Linux kernel commit a2770b57d083 ("dt-bindings: timer: Add CLINT bindings") adds the official DT bindings for CLINT, which uses "sifive,clint0" as the compatible string. "riscv,clint0" is now legacy and has to be kept for backward compatibility of legacy systems. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210430071302.1489082-3-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helperBin Meng2021-06-081-3/+3
| | | | | | | | | | | Since commit 78da6a1bca22 ("device_tree: add qemu_fdt_setprop_string_array helper"), we can use the new helper to set the clock name for the ethernet controller node. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210430071302.1489082-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw: Do not include qemu/log.h if it is not necessaryThomas Huth2021-05-021-1/+0
| | | | | | | | | | Many files include qemu/log.h without needing it. Remove the superfluous include statements. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210328054833.2351597-1-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* hw/riscv: Drop 'struct MemmapEntry'Bin Meng2021-03-041-7/+4
| | | | | | | | | | | There is already a MemMapEntry type defined in hwaddr.h. Let's drop the RISC-V defined `struct MemmapEntry` and use the existing one. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210220144807.819-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng2021-03-041-2/+41
| | | | | | | | | | | | | | | | | | This adds the QSPI2 controller to the SoC, and connects an SD card to it. The generation of corresponding device tree source fragment is also added. Specify machine property `msel` to 11 to boot the same upstream U-Boot SPL and payload image for the SiFive HiFive Unleashed board. Note subsequent payload is stored in the SD card image. $ qemu-system-riscv64 -nographic -M sifive_u,msel=11 -smp 5 -m 8G \ -bios u-boot-spl.bin -drive file=sdcard.img,if=sd Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-6-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng2021-03-041-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the QSPI0 controller to the SoC, and connects an ISSI 25WP256 flash to it. The generation of corresponding device tree source fragment is also added. Since the direct memory-mapped mode is not supported by the SiFive SPI model, the <reg> property does not populate the second group which represents the memory mapped address of the SPI flash. With this commit, upstream U-Boot for the SiFive HiFive Unleashed board can boot on QEMU 'sifive_u' out of the box. This allows users to develop and test the recommended RISC-V boot flow with a real world use case: ZSBL (in QEMU) loads U-Boot SPL from SPI flash to L2LIM, then U-Boot SPL loads the payload from SPI flash that is combined with OpenSBI fw_dynamic firmware and U-Boot proper. Specify machine property `msel` to 6 to allow booting from the SPI flash. U-Boot spl is directly loaded via `-bios`, and subsequent payload is stored in the SPI flash image. Example command line: $ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -smp 5 -m 8G \ -bios u-boot-spl.bin -drive file=spi-nor.img,if=mtd Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-5-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* riscv: Pass RISCVHartArrayState by pointerAlistair Francis2021-01-161-5/+5
| | | | | | | | | | | | | | We were accidently passing RISCVHartArrayState by value instead of pointer. The type is 824 bytes long so let's correct that and pass it by pointer instead. Fixes: Coverity CID 1438099 Fixes: Coverity CID 1438100 Fixes: Coverity CID 1438101 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Message-id: f3e04424723e0e222769991896cc82308fd23f76.1610751609.git.alistair.francis@wdc.com
* hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_typeBin Meng2021-01-161-5/+1
| | | | | | | | | | | SIFIVE_U_CPU is conditionally set to SIFIVE_U34 or SIFIVE_U54, hence there is no need to use #idef to set the mc->default_cpu_type. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210109143637.29645-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: Use the CPU to determine if 32-bitAlistair Francis2020-12-171-5/+5
| | | | | | | | | | | | | Instead of using string compares to determine if a RISC-V machine is using 32-bit or 64-bit CPUs we can use the initalised CPUs. This avoids us having to maintain a list of CPU names to compare against. This commit also fixes the name of the function to match the riscv_cpu_is_32bit() function. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 8ab7614e5df93ab5267788b73dcd75f9f5615e82.1608142916.git.alistair.francis@wdc.com
* hw/riscv: sifive_u: Remove compile time XLEN checksAlistair Francis2020-12-171-25/+30
| | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-id: 40d6df4dd05302c566e419be3a1fef7799e57c2e.1608142916.git.alistair.francis@wdc.com
* hw/riscv: boot: Remove compile time XLEN checksAlistair Francis2020-12-171-1/+1
| | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-id: 51e9842dbed1acceebad7f97bd3aae69aa1ac19e.1608142916.git.alistair.francis@wdc.com
* hw/riscv: sifive_u: Add UART1 DT node in the generated DTBAnup Patel2020-12-171-0/+15
| | | | | | | | | | | The sifive_u machine emulates two UARTs but we have only UART0 DT node in the generated DTB so this patch adds UART1 DT node in the generated DTB. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201111094725.3768755-1-anup.patel@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* vl: make qemu_get_machine_opts staticPaolo Bonzini2020-12-151-4/+2
| | | | | | | Machine options can be retrieved as properties of the machine object. Encourage that by removing the "easy" accessor to machine options. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* hw/riscv: sifive_u: Allow passing custom DTBAnup Patel2020-11-031-8/+20
| | | | | | | | | | | Extend sifive_u machine to allow passing custom DTB using "-dtb" command-line parameter. This will help users pass modified DTB or Linux SiFive DTB to sifive_u machine. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201022053225.2596110-1-anup.patel@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: Load the kernel after the firmwareAlistair Francis2020-10-221-2/+8
| | | | | | | | | | | | | | Instead of loading the kernel at a hardcoded start address, let's load the kernel at the next aligned address after the end of the firmware. This should have no impact for current users of OpenSBI, but will allow loading a noMMU kernel at the start of memory. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-id: 46c00c4f15b42feb792090e3d74359e180a6d954.1602634524.git.alistair.francis@wdc.com
* hw/riscv: sifive_u: Allow specifying the CPUAlistair Francis2020-10-221-5/+13
| | | | | | | | | | | Allow the user to specify the main application CPU for the sifive_u machine. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-id: b8412086c8aea0eff30fb7a17f0acf2943381b6a.1602634524.git.alistair.francis@wdc.com
* sifive_u: Register "start-in-flash" as class propertyEduardo Habkost2020-09-221-8/+8
| | | | | | | | | | Class properties make QOM introspection simpler and easier, as they don't require an object to be instantiated. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200921221045.699690-25-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* sifive_u: Rename memmap enum constantsEduardo Habkost2020-09-181-78/+78
| | | | | | | | | | | | | | Some of the enum constant names conflict with the QOM type check macros (SIFIVE_U_OTP, SIFIVE_U_PRCI). This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to SIFIVE_U_DEV_*, to avoid conflicts. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200911173447.165713-3-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* hw/riscv: Move sifive_uart model to hw/charBin Meng2020-09-091-1/+1
| | | | | | | | | | | This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_uart model to hw/char directory. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: Move sifive_plic model to hw/intcBin Meng2020-09-091-1/+1
| | | | | | | | | | | This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_plic model to hw/intc directory. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: Move sifive_clint model to hw/intcBin Meng2020-09-091-1/+1
| | | | | | | | | | | This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_clint model to hw/intc directory. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-6-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: sifive_u: Connect a DMA controllerBin Meng2020-09-091-0/+30
| | | | | | | | | | | SiFive FU540 SoC integrates a platform DMA controller with 4 DMA channels. This connects the exsiting SiFive PDMA model to the SoC, and adds its device tree data as well. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-17-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng2020-09-091-1/+2
| | | | | | | | | | | | | | At present the CLINT timestamp is using a hard-coded timebase frequency value SIFIVE_CLINT_TIMEBASE_FREQ. This might not be true for all boards. Add a new 'timebase-freq' property to the CLINT device, and update various functions to accept this as a parameter. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-16-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* target/riscv: cpu: Set reset vector based on the configured property valueBin Meng2020-09-091-0/+2
| | | | | | | | | | | | | Now that we have the newly introduced 'resetvec' property in the RISC-V CPU and HART, instead of hard-coding the reset vector addr in the CPU's instance_init(), move that to riscv_cpu_realize() based on the configured property value from the RISC-V machines. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-4-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: Allow creating multiple instances of PLICAnup Patel2020-08-251-1/+1
| | | | | | | | | | | | We extend PLIC emulation to allow multiple instances of PLIC in a QEMU RISC-V machine. To achieve this, we remove first HART id zero assumption from PLIC emulation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200616032229.766089-3-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: Allow creating multiple instances of CLINTAnup Patel2020-08-251-1/+1
| | | | | | | | | | | | We extend CLINT emulation to allow multiple instances of CLINT in a QEMU RISC-V machine. To achieve this, we remove first HART id zero assumption from CLINT emulation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-Id: <20200616032229.766089-2-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: Use pre-built bios image of generic platform for virt & sifive_uBin Meng2020-08-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update virt and sifive_u machines to use the opensbi fw_dynamic bios image built for the generic FDT platform. Remove the out-of-date no longer used bios images. Note: 1. To test 32-bit Linux kernel on QEMU 'sifive_u' 32-bit machine, the following patch is needed: http://lists.infradead.org/pipermail/linux-riscv/2020-July/001213.html 2. To test 64-bit Linux 5.3 kernel on QEMU 'virt' or 'sifive_u' 64-bit machines, the following commit should be cherry-picked to 5.3: commit 922b0375fc93fb1a20c5617e37c389c26bbccb70 Author: Albert Ou <aou@eecs.berkeley.edu> Date: Fri Sep 27 16:14:18 2019 -0700 riscv: Fix memblock reservation for device tree blob Linux 5.4 or above already contains this commit/fix. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1596439832-29238-5-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: sifive_u: Add a dummy L2 cache controller deviceBin Meng2020-08-211-0/+22
| | | | | | | | | | | It is enough to simply map the SiFive FU540 L2 cache controller into the MMIO space using create_unimplemented_device(), with an FDT fragment generated, to make the latest upstream U-Boot happy. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1595227748-24720-1-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw: Mark nd_table[] misuse in realize methods FIXMEMarkus Armbruster2020-07-211-0/+1
| | | | | | | | | | | | | | | nd_table[] contains NIC configuration for boards to pick up. Device code has no business looking there. Several devices do it anyway. Two of them already have a suitable FIXME comment: "allwinner-a10" and "msf2-soc". Copy it to the others: "allwinner-h3", "xlnx-versal", "xlnx,zynqmp", "sparc32-ledma", "riscv.sifive.u.soc". Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20200715140440.3540942-3-armbru@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* hw/riscv: Modify MROM size to end at 0x10000Bin Meng2020-07-131-1/+1
| | | | | | | | | | | At present the size of Mask ROM for sifive_u / spike / virt machines is set to 0x11000, which ends at an unusual address. This changes the size to 0xf000 so that it ends at 0x10000. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1594289144-24723-1-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* RISC-V: Support 64 bit start addressAtish Patra2020-07-131-1/+5
| | | | | | | | | | | | | Even though the start address in ROM code is declared as a 64 bit address for RV64, it can't be used as upper bits are set to zero in ROM code. Update the ROM code correctly to reflect the 64bit value. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-Id: <20200701183949.398134-5-atish.patra@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* riscv: Add opensbi firmware dynamic supportAtish Patra2020-07-131-5/+15
| | | | | | | | | | | | | | | | | | | | | | OpenSBI is the default firmware in Qemu and has various firmware loading options. Currently, qemu loader uses fw_jump which has a compile time pre-defined address where fdt & kernel image must reside. This puts a constraint on image size of the Linux kernel depending on the fdt location and available memory. However, fw_dynamic allows the loader to specify the next stage location (i.e. Linux kernel/U-Boot) in memory and other configurable boot options available in OpenSBI. Add support for OpenSBI dynamic firmware loading support. This doesn't break existing setup and fw_jump will continue to work as it is. Any other firmware will continue to work without any issues as long as it doesn't expect anything specific from loader in "a2" register. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-Id: <20200701183949.398134-4-atish.patra@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* RISC-V: Copy the fdt in dram instead of ROMAtish Patra2020-07-131-15/+13
| | | | | | | | | | | | | | | Currently, the fdt is copied to the ROM after the reset vector. The firmware has to copy it to DRAM. Instead of this, directly copy the device tree to a pre-computed dram address. The device tree load address should be as far as possible from kernel and initrd images. That's why it is kept at the end of the DRAM or 4GB whichever is lesser. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-Id: <20200701183949.398134-3-atish.patra@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>