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path: root/hw/riscv/sifive_u.c (follow)
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* target/riscv: support new isa extension detection devicetree propertiesConor Dooley2024-02-091-5/+2
* hw/riscv: use qemu_configure_nic_device()David Woodhouse2024-02-021-6/+1
* hw/sd: Introduce a "sd-card" SPI variant modelCédric Le Goater2023-09-011-2/+1
* hw/riscv: Move the dtb load bits outside of create_fdt()Bin Meng2023-03-011-16/+15
* hw/riscv: Skip re-generating DT nodes for a given DTBBin Meng2023-03-011-0/+1
* hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()Daniel Henrique Barboza2023-02-161-10/+1
* hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel()Daniel Henrique Barboza2023-02-161-1/+2
* hw/riscv: change riscv_compute_fdt_addr() semanticsDaniel Henrique Barboza2023-02-071-1/+2
* hw/riscv: split fdt address calculation from fdt loadDaniel Henrique Barboza2023-02-071-3/+4
* hw/riscv/sifive_u.c: simplify create_fdt()Daniel Henrique Barboza2023-01-201-4/+4
* hw/riscv/boot.c: use MachineState in riscv_load_kernel()Daniel Henrique Barboza2023-01-201-2/+1
* hw/riscv/boot.c: use MachineState in riscv_load_initrd()Daniel Henrique Barboza2023-01-201-2/+1
* hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel()Daniel Henrique Barboza2023-01-201-6/+5
* hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()Daniel Henrique Barboza2023-01-201-8/+2
* hw/riscv/sifive_u: use 'fdt' from MachineStateDaniel Henrique Barboza2023-01-201-9/+6
* hw/riscv/boot.c: introduce riscv_default_firmware_name()Daniel Henrique Barboza2023-01-201-7/+4
* hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"Bin Meng2023-01-061-1/+2
* hw/riscv: set machine->fdt in sifive_u_machine_init()Daniel Henrique Barboza2022-10-171-0/+3
* hw/riscv/sifive_u: Resolve redundant property accessorsBernhard Beschow2022-05-241-20/+4
* hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)Tsukasa OI2022-05-241-2/+2
* hw/riscv: Don't add empty bootargs to device treeBin Meng2022-04-291-1/+1
* hw/riscv: Use error_fatal for SoC realisationAlistair Francis2022-01-081-1/+1
* hw: Replace trivial drive_get_next() by drive_get()Markus Armbruster2021-12-151-1/+1
* hw/sd/ssi-sd: Do not create SD card within controller's realizeMarkus Armbruster2021-12-151-1/+12
* hw/riscv: sifive_u: Use the PLIC config helper functionAlistair Francis2021-10-281-13/+1
* hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_idBin Meng2021-10-221-4/+2
* hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel2021-09-211-3/+6
* hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel2021-09-211-1/+1
* sifive_u: Connect the SiFive PWM deviceAlistair Francis2021-09-211-1/+54
* hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis2021-09-211-1/+1
* arch_init.h: Don't include arch_init.h unnecessarilyPeter Maydell2021-08-261-1/+0
* hw/riscv: sifive_u: Make sure firmware info is 8-byte alignedBin Meng2021-07-151-2/+3
* hw/riscv: sifive_u: Correct the CLINT timebase frequencyBin Meng2021-07-151-2/+5
* hw/riscv: Use macros for BIOS image namesBin Meng2021-06-081-4/+2
* hw/riscv: Support the official PLIC DT bindingsBin Meng2021-06-081-1/+5
* hw/riscv: Support the official CLINT DT bindingsBin Meng2021-06-081-1/+5
* hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helperBin Meng2021-06-081-3/+3
* hw: Do not include qemu/log.h if it is not necessaryThomas Huth2021-05-021-1/+0
* hw/riscv: Drop 'struct MemmapEntry'Bin Meng2021-03-041-7/+4
* hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng2021-03-041-2/+41
* hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng2021-03-041-0/+52
* riscv: Pass RISCVHartArrayState by pointerAlistair Francis2021-01-161-5/+5
* hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_typeBin Meng2021-01-161-5/+1
* hw/riscv: Use the CPU to determine if 32-bitAlistair Francis2020-12-171-5/+5
* hw/riscv: sifive_u: Remove compile time XLEN checksAlistair Francis2020-12-171-25/+30
* hw/riscv: boot: Remove compile time XLEN checksAlistair Francis2020-12-171-1/+1
* hw/riscv: sifive_u: Add UART1 DT node in the generated DTBAnup Patel2020-12-171-0/+15
* vl: make qemu_get_machine_opts staticPaolo Bonzini2020-12-151-4/+2
* hw/riscv: sifive_u: Allow passing custom DTBAnup Patel2020-11-031-8/+20
* hw/riscv: Load the kernel after the firmwareAlistair Francis2020-10-221-2/+8