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path: root/include/hw/intc/loongarch_extioi.h (follow)
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* hw/intc/loongarch_extioi: Move unrealize function to common codeBibo Mao2025-07-111-1/+0
| | | | | | | | Memory about LoongArchExtIOICommonState::cpu is allocated in common code, it had better be freed in common code also. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
* hw/intc/loongarch_extioi: Add kernel irqchip save and restore functionBibo Mao2025-06-191-0/+2
| | | | | | | | | | Add save and store funtction if kvm_irqchip_in_kernel() return true, it is to get and set ExtIOI irqchip state from KVM kernel. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250606063033.2557365-3-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
* hw/intc/loongarch_extioi: Add kernel irqchip realize functionBibo Mao2025-06-191-0/+3
| | | | | | | | | | Function kvm_extioi_realize() is added if kvm_irqchip_in_kernel is set. It is to create and initialize ExtIOI device in kernel mode. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250606063033.2557365-2-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
* hw/intc/loongarch_extioi: Replace legacy reset callback with new apiBibo Mao2025-05-061-0/+1
| | | | | | | | | Replace legacy reset callback register device_class_set_legacy_reset() with new function resettable_class_set_parent_phases(). With new API, it will call reset callback of parent object and then itself. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
* hw/intc/loongarch_extioi: Code cleanup about loongarch_extioiBibo Mao2024-12-191-2/+0
| | | | | | | | | | Remove definition about LoongArchExtIOI and LOONGARCH_EXTIOI, and replace them with LoongArchExtIOICommonState and macro LOONGARCH_EXTIOI_COMMON separately. Also remove unnecessary header files. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
* hw/intc/loongarch_extioi: Inherit from loongarch_extioi_commonBibo Mao2024-12-191-2/+15
| | | | | | | | | Set TYPE_LOONGARCH_EXTIOI inherit from TYPE_LOONGARCH_EXTIOI_COMMON object, it shares vmsate and property of TYPE_LOONGARCH_EXTIOI_COMMON, and has its own realize() function. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
* include: Rename LoongArchExtIOI with LoongArchExtIOICommonStateBibo Mao2024-12-191-0/+1
| | | | | | | | Rename structure LoongArchExtIOI with LoongArchExtIOICommonState, since it is defined in file loongarch_extioi_common.h Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
* include: Move struct LoongArchExtIOI to header file loongarch_extioi_commonBibo Mao2024-12-191-26/+0
| | | | | | | | Move definiton of structure LoongArchExtIOI from header file loongarch_extioi.h to file loongarch_extioi_common.h. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
* include: Add loongarch_extioi_common header fileBibo Mao2024-12-191-49/+1
| | | | | | | | | Add common header file include/hw/intc/loongarch_extioi_common.h, and move some macro definition from include/hw/intc/loongarch_extioi.h to the common header file. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
* hw/loongarch: Remove unimplemented extioi INT_encode modeSong Gao2024-07-191-1/+0
| | | | | | | | Remove extioi INT_encode encode mode, because we don't emulate it. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Message-Id: <20240718083254.748179-1-gaosong@loongson.cn>
* hw/intc/loongarch_extioi: Add extioi virt extension definitionSong Gao2024-06-061-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On LoongArch, IRQs can be routed to four vcpus with hardware extended IRQ model. This patch adds the virt extension definition so that the IRQ can route to 256 vcpus. 1.Extended IRQ model: | +-----------+ +-------------|--------+ +-----------+ | IPI/Timer | --> | CPUINTC(0-3)|(4-255) | <-- | IPI/Timer | +-----------+ +-------------|--------+ +-----------+ ^ | | +---------+ | EIOINTC | +---------+ ^ ^ | | +---------+ +---------+ | PCH-PIC | | PCH-MSI | +---------+ +---------+ ^ ^ ^ | | | +--------+ +---------+ +---------+ | UARTs | | Devices | | Devices | +--------+ +---------+ +---------+ 2.Virt extended IRQ model: +-----+ +---------------+ +-------+ | IPI |--> | CPUINTC(0-255)| <-- | Timer | +-----+ +---------------+ +-------+ ^ | +-----------+ | V-EIOINTC | +-----------+ ^ ^ | | +---------+ +---------+ | PCH-PIC | | PCH-MSI | +---------+ +---------+ ^ ^ ^ | | | +--------+ +---------+ +---------+ | UARTs | | Devices | | Devices | +--------+ +---------+ +---------+ Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Message-Id: <20240528083855.1912757-2-gaosong@loongson.cn>
* hw/loongarch: fdt adds Extend I/O Interrupt ControllerSong Gao2024-04-291-0/+1
| | | | | | | | | | | | | fdt adds Extend I/O Interrupt Controller, we use 'loongson,ls2k2000-eiointc'. See: https://github.com/torvalds/linux/blob/v6.7/drivers/irqchip/irq-loongson-eiointc.c https://lore.kernel.org/r/764e02d924094580ac0f1d15535f4b98308705c6.1683279769.git.zhoubinbin@loongson.cn Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Message-Id: <20240426091551.2397867-12-gaosong@loongson.cn>
* hw/intc/loongarch_extioi: Add dynamic cpu number supportBibo Mao2024-01-111-3/+8
| | | | | | | | | | | | | | | | | | | | | On LoongArch physical machine, one extioi interrupt controller only supports 4 cpus. With processor more than 4 cpus, there are multiple extioi interrupt controllers; if interrupts need to be routed to other cpus, they are forwarded from extioi node0 to other extioi nodes. On virt machine model, there is simple extioi interrupt device model. All cpus can access register of extioi interrupt controller, however interrupt can only be route to 4 vcpu for compatible with old kernel. This patch adds dynamic cpu number support about extioi interrupt. With old kernel legacy extioi model is used, however kernel can detect and choose new route method in future, so that interrupt can be routed to all vcpus. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20231215100333.3933632-4-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
* hw/loongarch/virt: Set iocsr address space per-board rather than percpuBibo Mao2024-01-111-1/+0
| | | | | | | | | | | | | | | | | | LoongArch system has iocsr address space, most iocsr registers are per-board, however some iocsr register spaces banked for percpu such as ipi mailbox and extioi interrupt status. For banked iocsr space, each cpu has the same iocsr space, but separate data. This patch changes iocsr address space per-board rather percpu, for iocsr registers specified for cpu, MemTxAttrs.requester_id can be parsed for the cpu. With this patches, the total address space on board will be simple, only iocsr address space and system memory, rather than the number of cpu and system memory. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20231215100333.3933632-3-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
* hw/loongarch/virt: Set max 256 cpus support on loongarch virt machineSong Gao2023-05-151-4/+6
| | | | | | | | | | | | | | | Add separate macro EXTIOI_CPUS for extioi interrupt controller, extioi only supports 4 cpu. And set macro LOONGARCH_MAX_CPUS as 256 so that loongarch virt machine supports more cpus. Interrupts from external devices can only be routed cpu 0-3 because of extioi limits, cpu internal interrupt such as timer/ipi can be triggered on all cpus. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230512100421.1867848-3-gaosong@loongson.cn>
* hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)Xiaojuan Yang2022-06-061-0/+62
This patch realize the EIOINTC interrupt controller. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-35-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>