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path: root/include/hw/riscv/microchip_pfsoc.h (follow)
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* include: Include headers where neededMarkus Armbruster2023-01-081-0/+3
* hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0Bin Meng2023-01-061-1/+1
* hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLICBin Meng2023-01-061-1/+1
* hw/{misc, riscv}: pfsoc: add system controller as unimplementedConor Dooley2023-01-061-0/+1
* hw/riscv: pfsoc: add missing FICs as unimplementedConor Dooley2023-01-061-0/+2
* hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripheralsConor Dooley2022-09-071-1/+13
* hw/riscv: microchip_pfsoc: Use the PLIC config helper functionAlistair Francis2021-10-281-1/+0
* hw/riscv: microchip_pfsoc: Map EMMC/SD mux registerBin Meng2021-03-221-0/+1
* hw/riscv: microchip_pfsoc: add QSPI NOR flashVitaly Wool2020-12-171-0/+3
* hw/riscv: microchip_pfsoc: Hook the I2C1 controllerBin Meng2020-11-031-0/+1
* hw/riscv: microchip_pfsoc: Correct DDR memory mapBin Meng2020-11-031-1/+4
* hw/riscv: microchip_pfsoc: Map the reserved memory at address 0Bin Meng2020-11-031-0/+1
* hw/riscv: microchip_pfsoc: Connect the SYSREG moduleBin Meng2020-11-031-0/+2
* hw/riscv: microchip_pfsoc: Connect the IOSCB moduleBin Meng2020-11-031-1/+3
* hw/riscv: microchip_pfsoc: Connect DDR memory controller modulesBin Meng2020-11-031-0/+5
* hw/riscv: microchip_pfsoc: Hook GPIO controllersBin Meng2020-09-091-0/+3
* hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng2020-09-091-0/+7
* hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng2020-09-091-0/+11
* hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng2020-09-091-0/+4
* hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng2020-09-091-0/+20
* hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng2020-09-091-0/+88