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path: root/include/hw/riscv/sifive_e.h (follow)
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* hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b.Tommy Wu2023-07-101-3/+6
* hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0Bin Meng2023-01-061-1/+1
* hw/riscv: sifive_e: Fix the number of interrupt sources of PLICBin Meng2023-01-061-1/+6
* hw/riscv/sifive_e: Fix inheritance of SiFiveEStateBernhard Beschow2022-09-271-1/+2
* sifive_e: Rename memmap enum constantsEduardo Habkost2020-09-181-19/+19
* hw/riscv: Move sifive_gpio model to hw/gpioBin Meng2020-09-091-1/+1
* sifive_e: Support the revB machineAlistair Francis2020-06-191-0/+1
* riscv: Fix type of SiFive[EU]SocState, member parent_objMarkus Armbruster2020-06-151-1/+1
* riscv: sifive_e: Manually define the machineAlistair Francis2020-06-031-0/+4
* riscv: Add a sifive_cpu.h to include both E and U cpu type definesBin Meng2019-09-171-6/+1
* include: Make headers more self-containedMarkus Armbruster2019-08-161-0/+1
* RISC-V: Fix a memory leak when realizing a sifive_ePalmer Dabbelt2019-06-231-0/+2
* SiFive RISC-V GPIO DeviceFabien Chouteau2019-05-241-2/+6
* riscv: plic: Fix incorrect irq calculationAlistair Francis2019-04-041-1/+1
* hw/riscv/sifive_e: Create a SiFive E SoC objectAlistair Francis2018-07-051-2/+14
* RISC-V: Remove unused class definitionsMichael Clark2018-05-061-5/+0
* SiFive Freedom E Series RISC-V MachineMichael Clark2018-03-071-0/+79