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path: root/target/openrisc/interrupt.c (follow)
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* target/openrisc: Prefer fast cpu_env() over slower CPU QOM cast macroPhilippe Mathieu-Daudé2024-03-121-4/+2
* target/openrisc: Set EPCR to next PC on FPE exceptionsStafford Horne2023-07-311-3/+4
* gdbstub: move register helpers into standalone includeAlex Bennée2023-03-071-1/+1
* target/openrisc: Add interrupted CPU to logStafford Horne2022-09-041-1/+3
* exec/exec-all: Move 'qemu/log.h' include in units requiring itPhilippe Mathieu-Daudé2022-02-211-0/+1
* target/openrisc: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé2021-09-141-2/+0
* Include qemu-common.h exactly where neededMarkus Armbruster2019-06-121-1/+0
* target/openrisc: Fix LGPL information in the file headersThomas Huth2019-05-081-1/+1
* target/openrisc: Fix delay slot exception flag to match specStafford Horne2018-07-031-7/+12
* target/openrisc: Fix cpu_mmu_indexRichard Henderson2018-07-031-4/+0
* target/openrisc: Remove indirect function calls for mmuRichard Henderson2018-07-031-2/+0
* target/openrisc: Merge tlb allocation into CPUOpenRISCStateRichard Henderson2018-07-031-2/+2
* target/openrisc: Log interruptsRichard Henderson2018-07-031-5/+25
* target/openrisc: Support non-busy idle state using PMR SPRStafford Horne2017-05-041-0/+2
* target/openrisc: Implement EPH bitTim 'mithro' Ansell2017-04-211-0/+3
* target/openrisc: Implement EVBAR registerTim 'mithro' Ansell2017-04-211-1/+5
* target/openrisc: Tidy handling of delayed branchesRichard Henderson2017-02-141-2/+2
* target/openrisc: Keep SR_F in a separate variableRichard Henderson2017-02-141-1/+1
* target/openrisc: Implement lwa, swaRichard Henderson2017-02-141-0/+1
* target/openrisc: Fix exception handling status registersStafford Horne2017-02-141-0/+7
* cputlb: drop flush_global flag from tlb_flushAlex Bennée2017-01-131-1/+1
* Move target-* CPU file into a target/ folderThomas Huth2016-12-201-0/+87