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path: root/target/riscv/op_helper.c (follow)
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* target/riscv: Replace cpu_mmu_index with riscv_env_mmu_indexRichard Henderson2024-02-031-2/+2
* target/helpers: Remove unnecessary 'qemu/main-loop.h' headerPhilippe Mathieu-Daudé2023-08-311-1/+0
* target/translate: Include missing 'exec/cpu_ldst.h' headerPhilippe Mathieu-Daudé2023-08-311-0/+1
* target/riscv: Make MPV only work when MPP != PRV_MWeiwei Li2023-07-101-1/+2
* target/riscv: Check SUM in the correct registerRichard Henderson2023-05-051-1/+5
* target/riscv: Move hstatus.spvp check to check_access_hlsvRichard Henderson2023-05-051-1/+1
* target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BITRichard Henderson2023-05-051-1/+1
* target/riscv: Handle HLV, HSV via helpersRichard Henderson2023-05-051-6/+93
* target/riscv: Use cpu_ld*_code_mmu for HLVXRichard Henderson2023-05-051-2/+11
* target/riscv: Reduce overhead of MSTATUS_SUM changeFei Wu2023-05-051-2/+3
* target/riscv: fix H extension TVM trapYi Chen2023-05-051-6/+6
* target/riscv: Use PRV_RESERVED instead of PRV_HWeiwei Li2023-05-051-1/+1
* target/riscv: Fix the mstatus.MPP value after executing MRETWeiwei Li2023-05-051-1/+2
* target/riscv: Fix format for indentationWeiwei Li2023-05-051-2/+2
* target/riscv: Remove riscv_cpu_virt_enabled()Weiwei Li2023-05-051-9/+9
* target/riscv: Remove redundant check on RVHWeiwei Li2023-05-051-2/+1
* target/riscv: implement Zicbom extensionChristoph Muellner2023-03-051-0/+67
* target/riscv: implement Zicboz extensionChristoph Muellner2023-03-051-0/+68
* target/riscv: remove RISCV_FEATURE_PMPDaniel Henrique Barboza2023-03-011-1/+1
* RISC-V: Adding XTheadSync ISA extensionChristoph Müllner2023-02-071-0/+6
* target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+Bin Meng2023-01-061-0/+6
* target/riscv: Simplify helper_sret() a little bitBin Meng2023-01-061-14/+6
* target/riscv: Fix mret exception cause when no pmp rule is configuredBin Meng2023-01-061-1/+1
* target/riscv: rvk: add CSR support for ZkrWeiwei Li2022-04-291-0/+9
* compiler.h: replace QEMU_NORETURN with G_NORETURNMarc-André Lureau2022-04-211-2/+2
* target/riscv: Adjust csr write mask with XLENLIU Zhiwei2022-01-211-1/+2
* target/riscv: Don't save pc when exception returnLIU Zhiwei2022-01-211-2/+2
* target/riscv: helper functions to wrap calls to 128-bit csr insnsFrédéric Pétrot2022-01-081-0/+44
* target/riscv/pmp: fix no pmp illegal intrsNikita Shubin2022-01-081-1/+2
* target/riscv: Reorg csr instructionsRichard Henderson2021-09-011-11/+7
* target/riscv: fix wfi exception behaviorJose Martins2021-06-081-3/+8
* target/riscv: Use RISCVException enum for CSR accessAlistair Francis2021-05-111-9/+9
* hw: Do not include qemu/log.h if it is not necessaryThomas Huth2021-05-021-1/+0
* target/riscv/pmp: Raise exception if no PMP entry is configuredAtish Patra2021-01-161-0/+5
* target/riscv: Split the Hypervisor execute load helpersAlistair Francis2020-11-091-27/+9
* target/riscv: Remove the hyp load and store functionsAlistair Francis2020-11-091-86/+0
* target/riscv: Remove the HS_TWO_STAGE flagAlistair Francis2020-11-091-12/+0
* target/riscv: Set the virtualised MMU mode when doing hyp accessesAlistair Francis2020-11-091-13/+17
* target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang2020-11-031-7/+4
* target/riscv: Fix implementation of HLVX.WU instructionGeorg Kotheimer2020-10-221-3/+3
* riscv: Convert interrupt logs to use qemu_log_mask()Alistair Francis2020-10-221-1/+0
* target/riscv: Support the Virtual Instruction faultAlistair Francis2020-08-251-4/+38
* target/riscv: Return the exception from invalid CSR accessesAlistair Francis2020-08-251-6/+12
* target/riscv: Update the Hypervisor trap return/entryAlistair Francis2020-08-251-6/+2
* target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis2020-08-251-0/+114
* target/riscv: Implement checks for hfenceAlistair Francis2020-06-191-0/+13
* target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis2020-06-031-12/+5
* target/riscv: Correctly implement TSR trapAlistair Francis2020-03-161-1/+1
* target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis2020-02-271-1/+1
* target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis2020-02-271-0/+4