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* accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_coreRichard Henderson2024-12-243-2/+5
| | | | | | | | | Convert all targets simultaneously, as the gen_intermediate_code function disappears from the target. While there are possible workarounds, they're larger than simply performing the conversion. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Use float*_muladd_scalbnRichard Henderson2024-12-243-38/+54
| | | | | | | Use the scalbn interface instead of float_muladd_halve_result. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Merge tag 'exec-20241220' of https://github.com/philmd/qemu into stagingStefan Hajnoczi2024-12-216-72/+88
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Accel & Exec patch queue - Ignore writes to CNTP_CTL_EL0 on HVF ARM (Alexander) - Add '-d invalid_mem' logging option (Zoltan) - Create QOM containers explicitly (Peter) - Rename sysemu/ -> system/ (Philippe) - Re-orderning of include/exec/ headers (Philippe) Move a lot of declarations from these legacy mixed bag headers: . "exec/cpu-all.h" . "exec/cpu-common.h" . "exec/cpu-defs.h" . "exec/exec-all.h" . "exec/translate-all" to these more specific ones: . "exec/page-protection.h" . "exec/translation-block.h" . "user/cpu_loop.h" . "user/guest-host.h" . "user/page-protection.h" # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmdlnyAACgkQ4+MsLN6t # wN6mBw//QFWi7CrU+bb8KMM53kOU9C507tjn99LLGFb5or73/umDsw6eo/b8DHBt # KIwGLgATel42oojKfNKavtAzLK5rOrywpboPDpa3SNeF1onW+99NGJ52LQUqIX6K # A6bS0fPdGG9ZzEuPpbjDXlp++0yhDcdSgZsS42fEsT7Dyj5gzJYlqpqhiXGqpsn8 # 4Y0UMxSL21K3HEexlzw2hsoOBFA3tUm2ujNDhNkt8QASr85yQVLCypABJnuoe/// # 5Ojl5wTBeDwhANET0rhwHK8eIYaNboiM9fHopJYhvyw1bz6yAu9jQwzF/MrL3s/r # xa4OBHBy5mq2hQV9Shcl3UfCQdk/vDaYaWpgzJGX8stgMGYfnfej1SIl8haJIfcl # VMX8/jEFdYbjhO4AeGRYcBzWjEJymkDJZoiSWp2NuEDi6jqIW+7yW1q0Rnlg9lay # ShAqLK5Pv4zUw3t0Jy3qv9KSW8sbs6PQxtzXjk8p97rTf76BJ2pF8sv1tVzmsidP # 9L92Hv5O34IqzBu2oATOUZYJk89YGmTIUSLkpT7asJZpBLwNM2qLp5jO00WVU0Sd # +kAn324guYPkko/TVnjC/AY7CMu55EOtD9NU35k3mUAnxXT9oDUeL4NlYtfgrJx6 # x1Nzr2FkS68+wlPAFKNSSU5lTjsjNaFM0bIJ4LCNtenJVP+SnRo= # =cjz8 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 20 Dec 2024 11:45:20 EST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'exec-20241220' of https://github.com/philmd/qemu: (59 commits) util/qemu-timer: fix indentation meson: Do not define CONFIG_DEVICES on user emulation system/accel-ops: Remove unnecessary 'exec/cpu-common.h' header system/numa: Remove unnecessary 'exec/cpu-common.h' header hw/xen: Remove unnecessary 'exec/cpu-common.h' header target/mips: Drop left-over comment about Jazz machine target/mips: Remove tswap() calls in semihosting uhi_fstat_cb() target/xtensa: Remove tswap() calls in semihosting simcall() helper accel/tcg: Un-inline translator_is_same_page() accel/tcg: Include missing 'exec/translation-block.h' header accel/tcg: Move tcg_cflags_has/set() to 'exec/translation-block.h' accel/tcg: Restrict curr_cflags() declaration to 'internal-common.h' qemu/coroutine: Include missing 'qemu/atomic.h' header exec/translation-block: Include missing 'qemu/atomic.h' header accel/tcg: Declare cpu_loop_exit_requested() in 'exec/cpu-common.h' exec/cpu-all: Include 'cpu.h' earlier so MMU_USER_IDX is always defined target/sparc: Move sparc_restore_state_to_opc() to cpu.c target/sparc: Uninline cpu_get_tb_cpu_state() target/loongarch: Declare loongarch_cpu_dump_state() locally user: Move various declarations out of 'exec/exec-all.h' ... Conflicts: hw/char/riscv_htif.c hw/intc/riscv_aplic.c target/s390x/cpu.c Apply sysemu header path changes to not in the pull request. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * accel/tcg: Include missing 'exec/translation-block.h' headerPhilippe Mathieu-Daudé2024-12-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TB compile flags, tb_page_addr_t type, tb_cflags() and few other methods are defined in "exec/translation-block.h". All these files don't include "exec/translation-block.h" but include "exec/exec-all.h" which include it. Explicitly include "exec/translation-block.h" to be able to remove it from "exec/exec-all.h" later when it won't be necessary. Otherwise we'd get errors such: accel/tcg/internal-target.h:59:20: error: a parameter list without types is only allowed in a function definition 59 | void tb_lock_page0(tb_page_addr_t); | ^ accel/tcg/tb-hash.h:64:23: error: unknown type name 'tb_page_addr_t' 64 | uint32_t tb_hash_func(tb_page_addr_t phys_pc, vaddr pc, | ^ accel/tcg/tcg-accel-ops.c:62:36: error: use of undeclared identifier 'CF_CLUSTER_SHIFT' 62 | cflags = cpu->cluster_index << CF_CLUSTER_SHIFT; | ^ accel/tcg/watchpoint.c:102:47: error: use of undeclared identifier 'CF_NOIRQ' 102 | cpu->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(cpu); | ^ target/i386/helper.c:536:28: error: use of undeclared identifier 'CF_PCREL' 536 | if (tcg_cflags_has(cs, CF_PCREL)) { | ^ target/rx/cpu.c:51:21: error: incomplete definition of type 'struct TranslationBlock' 51 | cpu->env.pc = tb->pc; | ~~^ system/physmem.c:2977:9: error: call to undeclared function 'tb_invalidate_phys_range'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 2977 | tb_invalidate_phys_range(addr, addr + length - 1); | ^ plugins/api.c:96:12: error: call to undeclared function 'tb_cflags'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 96 | return tb_cflags(tcg_ctx->gen_tb) & CF_MEMI_ONLY; | ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241114011310.3615-5-philmd@linaro.org>
| * accel/tcg: Move tcg_cflags_has/set() to 'exec/translation-block.h'Philippe Mathieu-Daudé2024-12-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | The TranslationBlock flags are defined in 'exec/translation-block.h'. tcg_cflags_has/set() use them, it is more logical to declare them in the same place. Move them there too. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212144430.66224-2-philmd@linaro.org>
| * target/sparc: Move sparc_restore_state_to_opc() to cpu.cPhilippe Mathieu-Daudé2024-12-204-34/+42
| | | | | | | | | | | | | | | | | | | | | | | | Most targets define their restore_state_to_opc() handler in cpu.c. In order to keep SPARC aligned, move sparc_restore_state_to_opc() from translate.c to cpu.c. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20241115152053.66442-4-philmd@linaro.org> [PMD: Move definitions to new target/sparc/translate.h]
| * target/sparc: Uninline cpu_get_tb_cpu_state()Anton Johansson2024-12-202-37/+40
| | | | | | | | | | | | | | | | | | | | | | Required to compile accel/tcg/translate-all.c once for softmmu targets. The function gets quite big for some targets so uninlining makes sense. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Anton Johansson<anjo@rev.ng> Message-Id: <20240119144024.14289-14-anjo@rev.ng> [PMD: Only take SPARC part] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * accel/tcg: Move user-related declarations out of 'exec/cpu-all.h' (3/4)Philippe Mathieu-Daudé2024-12-201-0/+3
| | | | | | | | | | | | | | | | | | | | Move declarations related to page protection under user emulation from "exec/cpu-all.h" to "user/page-protection.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-14-philmd@linaro.org>
| * include: Rename sysemu/ -> system/Philippe Mathieu-Daudé2024-12-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Headers in include/sysemu/ are not only related to system *emulation*, they are also used by virtualization. Rename as system/ which is clearer. Files renamed manually then mechanical change using sed tool. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Message-Id: <20241203172445.28576-1-philmd@linaro.org>
* | include/hw/qdev-properties: Remove DEFINE_PROP_END_OF_LISTRichard Henderson2024-12-191-1/+0
|/ | | | | | | | | | | | | | Now that all of the Property arrays are counted, we can remove the terminator object from each array. Update the assertions in device_class_set_props to match. With struct Property being 88 bytes, this was a rather large form of terminator. Saves 30k from qemu-system-aarch64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Link: https://lore.kernel.org/r/20241218134251.4724-21-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target/sparc: Constify all Property and PropertyInfoRichard Henderson2024-12-151-2/+2
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Merge tag 'pull-tcg-20241212' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi2024-12-121-18/+8
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | tcg: Reset free_temps before tcg_optimize tcg/riscv: Fix StoreStore barrier generation include/exec: Introduce fpst alias in helper-head.h.inc target/sparc: Use memcpy() and remove memcpy32() # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmdbS7YdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9pFgf/RB1zSPYiID5psp+S # yL4raw8um4a3AbgI5g0wOY8PgIeN0anQxG0Yupo3Ka5rvhy9p7S36OOCJMFEJRbP # Sf2o4DG9Bqt6ycLh/mjQ8OqvL31T6f02GrkbUrevYVR7mYKjj+aJSbkIGKQqUOy3 # eptf9bbgtEe87oTXFZPxh24eEGE01WpHqDx3KQCCLlnsAR5ad9E8StWswu+8MiA/ # HttTGj8zqGu1N+wMtYfUuHtv8JdDK5H25gVbX/f+mLwNdWMXntsTw08Td3eY3EB0 # u44sEE+NSO04UiIu8U7NRrBNbUJsKautG90q4ZTOk5l8qVGIFWOP9kl0K1JjJZdd # jIR27g== # =+5lt # -----END PGP SIGNATURE----- # gpg: Signature made Thu 12 Dec 2024 15:46:46 EST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20241212' of https://gitlab.com/rth7680/qemu: target/sparc: Use memcpy() and remove memcpy32() include/exec: Introduce fpst alias in helper-head.h.inc tcg/riscv: Fix StoreStore barrier generation tcg: Reset free_temps before tcg_optimize Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * target/sparc: Use memcpy() and remove memcpy32()Philippe Mathieu-Daudé2024-12-121-18/+8
| | | | | | | | | | | | | | | | | | | | | | | | Rather than manually copying each register, use the libc memcpy(), which is well optimized nowadays. Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20241205205418.67613-1-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi2024-12-121-1/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * rust: better integration with clippy, rustfmt and rustdoc * rust: interior mutability types * rust: add a bit operations module * rust: first part of QOM rework * kvm: remove unnecessary #ifdef * clock: small cleanups, improve handling of Clock lifetimes # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmdZqFkUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroOzRwf/SYUD+CJCn2x7kUH/JG893jwN1WbJ # meGZ0PQDUpOZJFWg6T4g0MuW4O+Wevy2pF4SfGojgqaYxKBbTQVkeliDEMyNUxpr # vSKXego0K3pkX3cRDXNVTaXFbsHsMt/3pfzMQM6ocF9qbL+Emvx7Og6WdAcyJ4hc # lA17EHlnrWKUSnqN/Ow/pZXsa4ijCklXFFh4barfbdGVhMQc2QekUU45GsP2AvGT # NkXTQC05HqxBaAIDeSxbprDSzNihyT71dAooVoxqKboprPu5uoUSJwgaD8rADPr4 # EOfsz61V4mji+DWDcIzTtYoAdY41vVXI9lvCKOcCFkimA29xO0W6P7mG2w== # =JSh5 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 11 Dec 2024 09:57:29 EST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (49 commits) rust: qom: change the parent type to an associated type rust: qom: split ObjectType from ObjectImpl trait rust: qom: move bridge for TypeInfo functions out of pl011 rust: qdev: move bridge for realize and reset functions out of pl011 rust: qdev: move device_class_init! body to generic function, ClassInitImpl implementation to macro rust: qom: move ClassInitImpl to the instance side rust: qom: convert type_info! macro to an associated const rust: qom: rename Class trait to ClassInitImpl rust: qom: add default definitions for ObjectImpl rust: add a bit operation module rust: add bindings for interrupt sources rust: define prelude rust: cell: add BQL-enforcing RefCell variant rust: cell: add BQL-enforcing Cell variant bql: check that the BQL is not dropped within marked sections qom/object: Remove type_register() script/codeconverter/qom_type_info: Deprecate MakeTypeRegisterStatic and MakeTypeRegisterNotStatic ui: Replace type_register() with type_register_static() target/xtensa: Replace type_register() with type_register_static() target/sparc: Replace type_register() with type_register_static() ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | target/sparc: Replace type_register() with type_register_static()Zhao Liu2024-12-101-1/+1
| |/ | | | | | | | | | | | | | | | | Replace type_register() with type_register_static() because type_register() will be deprecated. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Link: https://lore.kernel.org/r/20241029085934.2799066-13-zhao1.liu@intel.com
* | target/sparc: Set default NaN pattern explicitlyPeter Maydell2024-12-111-0/+2
| | | | | | | | | | | | | | | | | | Set the default NaN pattern explicitly for SPARC, and remove the ifdef from parts64_default_nan. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241202131347.498124-50-peter.maydell@linaro.org
* | target/sparc: Initialize local scratch float_status from env->fp_statusPeter Maydell2024-12-113-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the helper functions flcmps and flcmpd we use a scratch float_status so that we don't change the CPU state if the comparison raises any floating point exception flags. Instead of zero-initializing this scratch float_status, initialize it as a copy of env->fp_status. This avoids the need to explicitly initialize settings like the NaN propagation rule or others we might add to softfloat in future. To do this we need to pass the CPU env pointer in to the helper. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241202131347.498124-33-peter.maydell@linaro.org
* | target/sparc: Set Float3NaNPropRule explicitlyPeter Maydell2024-12-111-0/+2
| | | | | | | | | | | | | | | | | | Set the Float3NaNPropRule explicitly for SPARC, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241202131347.498124-22-peter.maydell@linaro.org
* | target/sparc: Set FloatInfZeroNaNRule explicitlyPeter Maydell2024-12-111-0/+2
|/ | | | | | | | | Set the FloatInfZeroNaNRule explicitly for the SPARC target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241202131347.498124-10-peter.maydell@linaro.org
* target/sparc: Explicitly set 2-NaN propagation rulePeter Maydell2024-11-052-2/+16
| | | | | | | | | | Set the NaN propagation rule explicitly in the float_status words we use. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241025141254.2141506-13-peter.maydell@linaro.org
* target/sparc: Move cpu_put_fsr(env, 0) call to resetPeter Maydell2024-11-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Currently we call cpu_put_fsr(0) in sparc_cpu_realizefn(), which initializes various fields in the CPU struct: * fsr_cexc_ftt * fcc[] * fsr_qne * fsr It also sets the rounding mode in env->fp_status. This is largely pointless, because when we later reset the CPU this will zero out all the fields up until the "end_reset_fields" label, which includes all of these (but not fp_status!) Move the cpu_put_fsr(env, 0) call to reset, because that expresses the logical requirement: we want to reset FSR to 0 on every reset. This isn't a behaviour change because the fields are all zero anyway. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241025141254.2141506-12-peter.maydell@linaro.org
* license: Update deprecated SPDX tag LGPL-2.0+ to LGPL-2.0-or-laterPhilippe Mathieu-Daudé2024-09-202-2/+2
| | | | | | | | | | | | | | | | | | | The 'LGPL-2.0+' license identifier has been deprecated since license list version 2.0rc2 [1] and replaced by the 'LGPL-2.0-or-later' [2] tag. [1] https://spdx.org/licenses/LGPL-2.0+.html [2] https://spdx.org/licenses/LGPL-2.0-or-later.html Mechanical patch running: $ sed -i -e s/LGPL-2.0+/LGPL-2.0-or-later/ \ $(git grep -l 'SPDX-License-Identifier: LGPL-2.0+$') Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* target/sparc: Add gen_trap_if_nofpu_fpexceptionRichard Henderson2024-09-111-29/+61
| | | | | | | | | Model fp_exception state, in which only fp stores are allowed until such time as the FQ has been flushed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Carl Hauser <chauser@pullman.com>
* target/sparc: Implement STDFQRichard Henderson2024-09-112-3/+27
| | | | | | | | | | | Invalid encoding of addr should raise TT_ILL_INSN, so check before supervisor, which might raise TT_PRIV_INSN. Clear QNE after execution. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2340 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Carl Hauser <chauser@pullman.com>
* target/sparc: Add FSR_QNE to tb_flagsRichard Henderson2024-09-112-4/+14
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Carl Hauser <chauser@pullman.com>
* target/sparc: Populate sparc32 FQ when raising fp exceptionCarl Hauser2024-09-111-15/+25
| | | | | | | | | | | Implement a single instruction floating point queue, populated while delivering an fp exception. Signed-off-by: Carl Hauser <chauser@pullman.com> [rth: Split from a larger patch] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Carl Hauser <chauser@pullman.com>
* target/sparc: Add FQ and FSR.QNECarl Hauser2024-09-113-0/+51
| | | | | | | | | | | | | | Add support for, and migrate, a single-entry fp instruction queue for sparc32. Signed-off-by: Carl Hauser <chauser@pullman.com> [rth: Split from a larger patch; adjust representation with union; add migration state] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Carl Hauser <chauser@pullman.com>
* target/sparc: Restrict STQF to sparcv9Richard Henderson2024-08-202-2/+2
| | | | | | | | | | | Prior to sparcv9, the same encoding was STDFQ. Cc: qemu-stable@nongnu.org Fixes: 06c060d9e5b ("target/sparc: Move simple fp load/store to decodetree") Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240816072311.353234-2-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* sparc/ldst_helper: make range overlap check more readableYao Xingtao2024-07-231-3/+2
| | | | | | | | | | use ranges_overlap() instead of open-coding the overlap check to improve the readability of the code. Signed-off-by: Yao Xingtao <yaoxt.fnst@fujitsu.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240722040742.11513-9-yaoxt.fnst@fujitsu.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementationPeter Maydell2024-07-111-0/+1
| | | | | | | | | | | | | | | | | | Currently the TCGCPUOps::cpu_exec_halt method is optional, and if it is not set then the default is to call the CPUClass::has_work method (which has an identical function signature). We would like to make the cpu_exec_halt method mandatory so we can remove the runtime check and fallback handling. In preparation for that, make all the targets which don't need special handling in their cpu_exec_halt set it to their cpu_has_work implementation instead of leaving it unset. (This is every target except for arm and i386.) In the riscv case this requires us to make the function not be local to the source file it's defined in. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* target/sparc: use signed denominator in sdiv helperClément Chigot2024-06-191-1/+1
| | | | | | | | | | | | | The result has to be done with the signed denominator (b32) instead of the unsigned value passed in argument (b). Cc: qemu-stable@nongnu.org Fixes: 1326010322d6 ("target/sparc: Remove CC_OP_DIV") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2319 Signed-off-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240606144331.698361-1-chigot@adacore.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Enable VIS4 feature bitRichard Henderson2024-06-051-0/+3
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Implement monitor ASIsRichard Henderson2024-06-053-0/+16
| | | | | | | | Ignore the "monitor" portion and treat them the same as their base ASIs. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Implement MWAITRichard Henderson2024-06-052-0/+12
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Implement SUBXC, SUBXCccRichard Henderson2024-06-052-0/+16
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Implement FPMIN, FPMAXRichard Henderson2024-06-052-0/+28
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Implement VIS4 comparisonsRichard Henderson2024-06-054-47/+153
| | | | | | | | VIS4 completes the set, adding missing signed 8-bit ops and missing unsigned 16 and 32-bit ops. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Implement 8-bit FPADD, FPADDS, and FPADDUSRichard Henderson2024-06-052-0/+20
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Implement FALIGNDATAiRichard Henderson2024-06-052-3/+31
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Add feature bit for VIS4Richard Henderson2024-06-052-0/+3
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Implement IMA extensionRichard Henderson2024-06-054-0/+31
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Enable VIS3 feature bitRichard Henderson2024-06-051-0/+3
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Implement XMULXRichard Henderson2024-06-054-0/+19
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Implement UMULXHIRichard Henderson2024-06-052-0/+9
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Implement PDISTNRichard Henderson2024-06-052-0/+12
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOdRichard Henderson2024-06-052-0/+42
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Implement LZCNTRichard Henderson2024-06-052-0/+19
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Implement LDXEFSRRichard Henderson2024-06-054-2/+17
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Implement FSLL, FSRL, FSRA, FSLASRichard Henderson2024-06-054-0/+58
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8Richard Henderson2024-06-054-0/+58
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>