diff options
| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2014-09-05 11:30:05 +0200 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2014-09-05 11:30:05 +0200 |
| commit | 6e09df71a333bf87cd68c2d08ad068a3e501462d (patch) | |
| tree | 7d76e0626e61ef5a9f15c62358337674fb0095aa /miasm2/analysis/debugging.py | |
| parent | e8d0fcf8d28d82a8f33138d044f335634ac3a30c (diff) | |
| download | miasm-6e09df71a333bf87cd68c2d08ad068a3e501462d.tar.gz miasm-6e09df71a333bf87cd68c2d08ad068a3e501462d.zip | |
Modify irbloc destination mecanism. Rework API in consequence.
Fat patch here: some API have changed. Each irbloc now affects a special "IRDst" register which is used to describe the destination irbloc. It allows simple description of architectures using delay slots. Architectures semantic and tcc/python jitter are modified in consequence. LLVM jitter is disabled for now, but should be patch soon.
Diffstat (limited to 'miasm2/analysis/debugging.py')
| -rw-r--r-- | miasm2/analysis/debugging.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/miasm2/analysis/debugging.py b/miasm2/analysis/debugging.py index 28e5ab3c..82710b6a 100644 --- a/miasm2/analysis/debugging.py +++ b/miasm2/analysis/debugging.py @@ -190,7 +190,7 @@ class Debugguer(object): def set_reg_value(self, reg_name, value): # Handle PC case - if reg_name == self.myjit.my_ir.pc.name: + if reg_name == self.myjit.ir_arch.pc.name: self.init_run(value) setattr(self.myjit.cpu, reg_name, value) |