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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-05-30 16:52:07 +0200 |
|---|---|---|
| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-05-30 16:52:17 +0200 |
| commit | 9260319e7411ff8281700a532caa436f40120ec4 (patch) | |
| tree | 2f6bfe5f3458dd49d328d3a9eb508595450adec0 /gitlab/issues_text/target_i386/host_missing/accel_missing/1164 | |
| parent | 225caa38269323af1bfc2daadff5ec8bd930747f (diff) | |
| download | qemu-analysis-9260319e7411ff8281700a532caa436f40120ec4.tar.gz qemu-analysis-9260319e7411ff8281700a532caa436f40120ec4.zip | |
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Diffstat (limited to 'gitlab/issues_text/target_i386/host_missing/accel_missing/1164')
| -rw-r--r-- | gitlab/issues_text/target_i386/host_missing/accel_missing/1164 | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/gitlab/issues_text/target_i386/host_missing/accel_missing/1164 b/gitlab/issues_text/target_i386/host_missing/accel_missing/1164 new file mode 100644 index 000000000..d79ec6483 --- /dev/null +++ b/gitlab/issues_text/target_i386/host_missing/accel_missing/1164 @@ -0,0 +1,17 @@ +q35: incorrect values for PCIEXBAR masks +Description of problem: +https://lore.kernel.org/all/1fded151ce5ecbf7010427871b908000b2aba9ee.1520867956.git.x1917x@gmail.com/ + +In function [mch_update_pciexbar](https://gitlab.com/qemu-project/qemu/-/blob/master/hw/pci-host/q35.c#L295) + +There are two small issues in PCIEXBAR address mask handling: +- wrong bit positions for address mask bits (see PCIEXBAR description + in Q35 datasheet) +- incorrect usage of 64ADR_MASK + +Due to this, attempting to write a valid PCIEXBAR address may cause it to +shift to another address, causing memory layout corruption where emulated +MMIO regions may overlap real (passed through) MMIO ranges. Fix this +by providing correct values. +Additional information: +Q35 datasheet: https://www.intel.com/Assets/PDF/datasheet/316966.pdf ( 5.1.16 PCIEXBAR—PCI Express* Register Range Base Address ) |