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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-05-30 16:52:07 +0200 |
|---|---|---|
| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-05-30 16:52:17 +0200 |
| commit | 9260319e7411ff8281700a532caa436f40120ec4 (patch) | |
| tree | 2f6bfe5f3458dd49d328d3a9eb508595450adec0 /gitlab/issues_text/target_riscv/host_missing/accel_missing/2787 | |
| parent | 225caa38269323af1bfc2daadff5ec8bd930747f (diff) | |
| download | qemu-analysis-9260319e7411ff8281700a532caa436f40120ec4.tar.gz qemu-analysis-9260319e7411ff8281700a532caa436f40120ec4.zip | |
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Diffstat (limited to 'gitlab/issues_text/target_riscv/host_missing/accel_missing/2787')
| -rw-r--r-- | gitlab/issues_text/target_riscv/host_missing/accel_missing/2787 | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/gitlab/issues_text/target_riscv/host_missing/accel_missing/2787 b/gitlab/issues_text/target_riscv/host_missing/accel_missing/2787 new file mode 100644 index 000000000..a403a165a --- /dev/null +++ b/gitlab/issues_text/target_riscv/host_missing/accel_missing/2787 @@ -0,0 +1,13 @@ +Opentitan timer layout incorrect +Description of problem: +It looks as if some of the timer register offsets here are incorrect: + +https://gitlab.com/qemu-project/qemu/-/blob/master/hw/timer/ibex_timer.c?ref_type=heads#L37 + +Compare with: + +https://opentitan.org/book/hw/ip/rv_timer/doc/registers.html + +I suspect they're out of date. The documentation link on line 7 is not working anymore - the current documentation URL for Opentitan is the one just given. + +It might also make sense to rename this file `opentitan_timer.c`, instead of `ibex_timer.c`. The timer is an Opentitan hardware IP block, rather than a feature of the Ibex CPU. |