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RISC-V priviledged instruction error
Hello when performing an MRET with MPP set to something else than 0b11 in MSTATUS, 'Invalid Instruction' exception will be triggered. The problem appeared in code after version 5.2.0.
<pre>
# setup interrupt handling for monitor mode
la t0, entry_loop
la t1, entry_trap
li t2, 0x888
li t3, 0x1880 # MPP in MSTATUS selects to which mode to return & MPIE selects if to enable interrupts after MRET
csrw mepc, t0
csrw mtvec, t1
csrs mie, t2
csrs mstatus, t3
# if supervisor mode not supported, then loop forever
csrr t0, misa
li t1, 0x40000
and t2, t1, t0
beqz t2, 1f
# setup interrupt i& exception delegation for supervisor mode
li t0, 0xc0000000 # 3 GiB (entry address of supervisor)
li t1, 0x1000
#li t2, 0x300 # bit 8 & 9 is for ecall from user & supervisor mode
#li t3, 0x222
csrw mepc, t0
csrc mstatus, t1
#csrs medeleg, t2
#csrs mideleg, t3
# pass mhartid as first parameter to supervisor
csrr a0, mhartid
1:
mret
</pre>
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