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* [RV64_DYNAREC] Fixed flags for shrd/shld with constant 0 shift (#1730)Yang Liu2024-08-101-13/+23
* [RV64_DYNAREC] Fixed ROL/ROR RCX, CL (#1729)xctan2024-08-102-22/+14
* Added 67.AVX.0F.66 D6 opcode ([ARM64_DYNAREC] too)ptitSeb2024-08-101-0/+21
* Added 64bits 67 F3 0F 7F opcode ([ARM64_DYNAREC] too)ptitSeb2024-08-101-0/+13
* [ARM64_DYNAREC] Fixed flags for surd/shld with constant 0 shiftptitSeb2024-08-101-12/+22
* [ARM64_DYNAREC] Fixed pending flags for large 8 & 16 bit const shiftsptitSeb2024-08-101-0/+6
* [RV64_DYNAREC] Fixed pending flags for large 8 & 16 bit const shifts (#1728)xctan2024-08-101-0/+6
* [RV64_DYNAREC] Fixed more register conflicts (#1726)Yang Liu2024-08-093-8/+8
* [RV64_DYNAREC] Fixed OF generation in emit_sar16c (#1724)xctan2024-08-091-10/+4
* [ARM64_DYNAREC] Added AVX.66.0F38 9A opcodeptitSeb2024-08-091-2/+13
* [RV64_DYNAREC] Fixed fpu_flags handling and enabled cosim in CI (#1722)Yang Liu2024-08-091-0/+3
* [RV64_DYNAREC] Fixed misused BNE_NEXT in emit_ro{l,r}32 (#1723)xctan2024-08-091-4/+6
* [RV64_DYNAREC] Fixed FNSTSW opcode (#1721)Yang Liu2024-08-092-0/+5
* [DYNAREC_RV64] Removed TODOs on GETEX and GETEM macros (#1720)Yang Liu2024-08-096-306/+303
* [RV64_DYNAREC] Fixed register conflict in the GETSEB marco (#1719)xctan2024-08-091-1/+1
* [RV64_DYNAREC] Fixed register conflict with GETEB macro (#1718)xctan2024-08-081-7/+14
* [LA64_DYNAREC] Fixed flag generation in IMUL/MUL opcode (#1716)Yang Liu2024-08-083-65/+100
* [RV64_DYNAREC] Fixed flag generation in IMUL/MUL opcode (#1715)xctan2024-08-084-12/+39
* [ARM64_DYNAREC] Added AVX.F3.0F38 F7 opcodeptitSeb2024-08-073-0/+82
* [ARM64_DYNAREC] Added F0 20 opcodeptitSeb2024-08-041-0/+31
* [DYNAREC] Remove BARRIER_NEXT macroptitSeb2024-07-2911-27/+0
* Added 67 66 0F FE opcode ([ARM64_DYNAREC] too)ptitSeb2024-07-231-0/+8
* [RV64_DYNAREC] Fixed more issues in the vector infrastructure (#1706)Yang Liu2024-07-233-5/+9
* [RV64_DYNAREC] Fixed vector infra (#1705)Yang Liu2024-07-224-32/+51
* [DYNAREC] Fixed CI failures for RV64 and LA64 (#1702)Yang Liu2024-07-222-11/+14
* Improved exception/int 3 handlingptitSeb2024-07-213-7/+27
* [ARM64_DYNAREC] Add a test about arm64 addresses in pass3, and abort if wrongptitSeb2024-07-211-0/+1
* [DYNAREC] Fixed a typo in an error messageptitSeb2024-07-211-2/+2
* [LA64_DYNAREC] Added more opcodes (#1701)Yang Liu2024-07-205-722/+811
* [LA64_DYNAREC] Added more opcodes (#1700)Yang Liu2024-07-205-0/+131
* [RV64_DYNAREC] Added more 66 0F 38 opcodes for vector (#1699)Yang Liu2024-07-192-0/+34
* [RV64_DYNAREC] Added vector SEW cache (#1698)Yang Liu2024-07-1915-76/+143
* [RV64_DYNAREC] Added 66 0F 38 00 PSHUFB for vector (#1697)Yang Liu2024-07-183-4/+32
* [RV64_DYNAREC] Added more 66 0F opcodes for vector (#1696)Yang Liu2024-07-182-0/+47
* [RV64_DYNAREC] Show missing opcodes in vector implementation (#1695)Yang Liu2024-07-183-3/+22
* [LA64_DYNAREC] Added more opcodes and fixed more issues (#1692)Yang Liu2024-07-174-6/+90
* [LA64_DYNAREC] Added more opcodes (#1690)Yang Liu2024-07-172-3/+95
* [LA64_DYNAREC] Added more opcodes (#1688)Yang Liu2024-07-163-0/+90
* [LA64_DYNAREC] Fixed CMPSD (#1687)Yang Liu2024-07-161-1/+1
* [LA64_DYNAREC] Fixed some opcodes (#1686)Yang Liu2024-07-162-3/+9
* [RV64_DYNAREC] Fixed GETGXSS_empty on upper bits handling (#1685)Yang Liu2024-07-161-2/+1
* [RV64_DYNAREC] Clear high 32bits when write back as single (#1684)Yang Liu2024-07-161-2/+5
* [LA64_DYNAREC] Remove xMASK and fixed 86 XCHG opcode (#1683)Yang Liu2024-07-1613-90/+67
* [ARM64_DYNAREC] Fixed OR Ew, Gw (#1682)Yang Liu2024-07-161-1/+1
* [RV64_DYNAREC] Fixed some bugs for VMP (#1679)xctan2024-07-165-49/+41
* [LA64_DYNAREC] Added 2 more opcodes (#1680)Yang Liu2024-07-152-0/+21
* [RV64_DYNAREC] Cleanup for removed rv64_lock_cas_dq (#1670)Ivan Melnikov2024-07-112-4/+0
* [ARM64_DYNAREC] Added handling of FASTNAN=0 to MULSS opcodeptitSeb2024-07-111-4/+17
* fix some spelling (#1668)josch2024-07-1010-24/+24
* [DYNAREC] Fixed `ymm0_purge` for some instructions (#1664)rajdakin2024-07-101-2/+6