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* Merge pull request #2692 from ksco/wow64André Zwing2025-05-301-1/+1
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| * [WOW64] Improved RIP handling on INT nYang Liu2025-05-311-1/+1
* | [DYNAREC] Fixed a prefix typo in dynarec dump (#2693)Yang Liu2025-05-301-1/+1
* | This should fix the WoW buildptitSeb2025-05-301-2/+2
* | [ARM64_DYNAREC] Try to optimise Windows INT n version on 64bits (TODO: Interp...ptitSeb2025-05-303-1/+8
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* [DYNAREC] Ported 37ed49cb to RV64 and LA64 (#2690)Yang Liu2025-05-302-2/+4
* [TRACE][ARM64_DYNAREC] Fixed potential buffer overflow on dynarec_dump scenarioptitSeb2025-05-301-1/+2
* [ARM64_DYNAREC] Small improvment on Wine INT n handlingptitSeb2025-05-301-5/+13
* [WOW64] Added support for cosim (#2683)Yang Liu2025-05-302-1/+6
* [WOW64] Added more missing pieces and the interpreter works (#2682)Yang Liu2025-05-291-3/+3
* [ARM64_DYNAREC] More optimisation of unused XMM/YMM purgeptitSeb2025-05-282-10/+28
* [ARM64_DYNAREC] Optimized a bit CVTTPS2DQ on fastround=0 when frintts is not ...ptitSeb2025-05-281-1/+18
* [ARM64_DYNAREC] Small optim to modreg CMPXCHG (#2680)Yang Liu2025-05-282-13/+15
* [WOW64] Supported logging to stdout (#2679)Yang Liu2025-05-281-2/+2
* [ARM64_DYNAREC] Fixed a warning (#2678)Yang Liu2025-05-281-1/+1
* [DYNAREC] Fixed expected return address in bridged native call (#2677)Yang Liu2025-05-282-2/+2
* [RV64_DYNAREC] Fixed regression introduced in #2669 (#2676)Yang Liu2025-05-274-28/+30
* [RV64_DYNAREC] Removed useless zero-ups in some emit_* functions (#2672)Yang Liu2025-05-262-20/+41
* [RV64_DYNAREC] Added more opcodes to printer (#2671)Yang Liu2025-05-261-0/+220
* [RV64_DYNAREC] Improved ret_to_epilog with xtheadmemidx (#2670)Yang Liu2025-05-262-61/+83
* [RV64_DYNAREC] Minor nativeflags optim to LEA and CMOVcc opcodes (#2669)Yang Liu2025-05-266-28/+118
* [RV64_DYNAREC] Improved emit_pf with Zbb (#2665)Yang Liu2025-05-231-7/+11
* [RV64_DYNAREC] Optimized CLZ macro with xtheadbb (#2664)Yang Liu2025-05-232-40/+48
* [RV64_DYNAREC] Optimized some opcodes with xtheadbb (#2663)Yang Liu2025-05-233-29/+47
* [WOW64] Implement syscallsAndré Zwing2025-05-221-0/+19
* [WOW64] Don't check the protection on win32André Zwing2025-05-221-0/+2
* [ARM64_DYNAREC] Try to avoid Load/Unload of XMM/YMM regs when possible on int...ptitSeb2025-05-226-26/+121
* [RV64_DYNAREC] Enable nativeflags optimization for more patterns (#2659)Yang Liu2025-05-2216-176/+201
* [ARM64_DYNAREC] Fix (and small optim) on VPMASKMOVD/VPMASKMOVQ opcodesptitSeb2025-05-211-8/+8
* [RV64_DYNAREC] Fixed a typo in 66 F0 0F LOCK CMPXCHG opcode (#2658)Yang Liu2025-05-211-1/+1
* [RV64_DYNAREC] Implemented unaligned path for LOCK INC/DEC opcodes (#2656)Yang Liu2025-05-211-8/+34
* [DYNAREC] Removed unnecessary volatile metadata barriers (#2653)Yang Liu2025-05-201-12/+4
* [RV64_DYNAREC] Fixed more potential scratch register conflicts (#2652)Yang Liu2025-05-202-5/+5
* [RV64_DYNAREC] Improved POPCNT and fixed some scratch conflicts (#2651)Yang Liu2025-05-206-34/+95
* [WOW64] Implement BTCpuSimulateAndré Zwing2025-05-192-0/+6
* [ARM64_DYNAREC] Added fastnan=0 handling to 0F 52 opcodeptitSeb2025-05-182-15/+13
* [RV64_DYNAREC] Enabled native flags optimization for SETcc opcodes (#2640)Yang Liu2025-05-164-30/+87
* [RV64_DYNAREC] Added F2 0F F0 LDDQU opcode for vector (#2639)Yang Liu2025-05-151-0/+18
* [DYNAREC] Fixed alternate address testing when retriving dynablock (#2638)Yang Liu2025-05-152-4/+3
* [RV64_DYNAREC] Added more opcodes for vector (#2637)Yang Liu2025-05-152-1/+30
* [DYNAREC] More minor changes to missing VEX prefixed opcodes (#2636)Yang Liu2025-05-152-2/+3
* [ARM64_DYNAREC][TRACE] Yet another small change on DYNAREC_MISSING=1 handling...ptitSeb2025-05-151-1/+1
* [ARM64_DYNAREC][TRACE] Anothor small change on DYNAREC_MISSING=1 handling of ...ptitSeb2025-05-151-1/+1
* [ARM64_DYNAREC][TRACE] Improved DYNAREC_MISSING=1 handling of missing VEX pre...ptitSeb2025-05-151-2/+2
* [RV64_DYNAREC] Added and optimized some SSE/MMX opcodes (#2635)Yang Liu2025-05-152-45/+60
* [RV64_DYNAREC] Fixed a typo introduced lately (#2634)Yang Liu2025-05-141-1/+1
* [RV64_DYNAREC] Added more mmx opcodes (#2629)Yang Liu2025-05-142-9/+68
* [RV64_DYNAREC] Added more mmx opcodes (#2630)Yang Liu2025-05-131-1/+41
* [RV64_DYNAREC] Added more mmx opcodes (#2627)Yang Liu2025-05-131-3/+39
* [RV64_DYNAREC] Added more mmx opcodesYang Liu2025-05-132-1/+112