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* [ARM64_DYNAREC] Fixed 8C opcodeptitSeb2024-02-161-1/+3
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* [ARM64_DYNAREC][32BITS] Added C4 /m and C5 /m opcodesptitSeb2024-02-161-1/+28
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* [ARM64_DYNAREC] Added 0F A0/A1/A8/A9 opcodesptitSeb2024-02-161-1/+23
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* [ARM64_DYNAREC] Added better handling for DD C0 D9 F7 sequenceptitSeb2024-02-161-1/+7
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* [ARM64_DYNAREC] Improved FFREE handling (fixing gameplay of Serious Sam 2, ↵ptitSeb2024-02-115-19/+115
| | | | probably some other game too)
* [ARM64_DYNAREC] Improved FFREE/FXAM opcodes (helps 32bits games like ↵ptitSeb2024-02-113-3/+29
| | | | SeriousSam2)
* Added 0F 01 E0..E7 opcodes ([ARM64_DYNAREC] too)ptitSeb2024-02-101-0/+12
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* [ARM64_DYNAREC] Added F0 21 opcodeptitSeb2024-02-081-0/+33
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* [ARM64_DYNAREC] Improved stability when USCAT extention is supported, qn d ↵ptitSeb2024-02-072-23/+98
| | | | improved reliqbility of unaligned fallback for LOCK CMPXCHG8B/CMPXCHG16B opcodes
* [ARM64_DYNAREC] 32bits Shift with 0 amount still wipe upper part of register ↵ptitSeb2024-02-071-5/+30
| | | | on 64bits
* [DYNAREC] Tests for emited coded size limit (usefull for DYNAREC_TEST for ↵ptitSeb2024-02-074-2/+15
| | | | example)
* [DYNAREC_RV64] f23 and f24 are save in a same place (#1251)factfinding2024-02-071-1/+1
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* [ARM64_DYNAREC] Added 0F C7 /1 opcodeptitSeb2024-02-071-1/+34
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* [ARM64_DYNAREC] More fixes to F0 0F C7 opcodeptitSeb2024-02-072-74/+70
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* [ARM64_DYNAREC] Fixed F0 0F C7 opcode that was broken on previous commitptitSeb2024-02-061-7/+7
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* [ARM64_DYNAREC] Reworked, again, strongmem emulationptitSeb2024-02-062-5/+15
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* [ARM64_DYNAREC] Added an unaligned path for F0 0F C7 /1 opcodeptitSeb2024-02-061-0/+36
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* Changed a bit how SGDT/SIDT are faked ([ARM64_DYNAREC] too)ptitSeb2024-02-061-5/+13
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* [ARM64_DYNAREC] Added BOX64_DYNAREC_DIV0 option to check/trigger Divide by 0 ↵ptitSeb2024-02-053-1/+161
| | | | when needed
* [ARM64_DYANREC] Try to fix DD /1 opcode with FRINT extensionptitSeb2024-02-041-1/+1
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* [RV64_DYNAREC] Fixed buildptitSeb2024-02-041-1/+1
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* [RV64_DYNAREC][32BITS] Added optim for 32bits jumptable and fix buildptitSeb2024-02-046-22/+28
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* [ARM64_DYNAREC][32BITS] Small optim on jump table for 32bits access (1 less ↵ptitSeb2024-02-047-34/+40
| | | | read, or 2 in SAVE_MEM configuration)
* [ARM64_DYNAREC] Small D8..DF opcodes refactorptitSeb2024-02-048-1029/+938
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* [ARM64_DYNAREC] Reworked STRONGMEM 2 & 3ptitSeb2024-02-036-19/+89
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* [ARM64_DYNAREC] Improved 0F AE opcodesptitSeb2024-02-031-27/+24
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* [ARM64_DYNAREC] DD /6 opcode also perform x87 initptitSeb2024-02-031-1/+2
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* [ARM64_DYNAREC] Use frint extension for DD /1 opcodeptitSeb2024-02-031-18/+17
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* Added 0F 0E opcode support ([ARM64_DYNAREC] too)ptitSeb2024-02-011-0/+11
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* [32BITS] Added 67 64 89 opcode ([ARM64_DYNAREC] too)ptitSeb2024-02-011-0/+13
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* [32BITS] Added 67 64 A1 opcode ([ARM64_DYNAREC] too)ptitSeb2024-02-011-0/+14
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* [DYNAREC] Handling of memfd_create backed mmap on dynarec (help #1234 but ↵ptitSeb2024-02-012-2/+9
| | | | doesn't solve it completly)
* [RV64_DYNAREC] Fixed 0F AF 32bits (for #1210)ptitSeb2024-01-301-0/+9
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* [ARM64_DYNAREC] Added UDF printerptitSeb2024-01-301-0/+5
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* [ARM64_DYNAREC] Small changes on 32BITS E9 opcode to ensure 32bits jump ↵ptitSeb2024-01-301-2/+7
| | | | destination
* [RV64_DYNAREC] Fixed some isue wiht sse_get_reg helper function tht would ↵ptitSeb2024-01-291-11/+13
| | | | incorectly mark a regs as changed single/non-single
* [ARM64_DYNAREC] ROL/ROR/RCL/RCR might not update OF if count is not 1ptitSeb2024-01-292-13/+55
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* [ARM64_DYNAREC] Small improvments to SHLD/SHRD helpersptitSeb2024-01-291-21/+15
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* [ARM64_DYNAREC] Fixed 66 50-5F opcodes (helps Dave the Diver)ptitSeb2024-01-291-2/+2
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* [TRACE] Slightly better trace for some dynarec runtime issuesptitSeb2024-01-291-1/+1
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* [ARM64_DYNAREC] Added 67 6B opcodeptitSeb2024-01-291-0/+34
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* [ARM64_DYNAREC] Added F0 0F C0 opcodeptitSeb2024-01-291-0/+46
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* [DYNAREC] Small improvment in dynablock/protectDB handlingptitSeb2024-01-291-10/+8
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* [ARM64_DYNAREC] Removed old unused codeptitSeb2024-01-291-20/+0
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* Added BOX64_IGNOREINT3 env. var. to ignore INT3 in the code ([RCFILE] too)ptitSeb2024-01-272-30/+26
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* [ARM64_DYNAREC] Added E4/E5/E6/E7 opcodesptitSeb2024-01-271-2/+16
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* [ARM64_DYNAREC][32BITS] Added D4/D5 opcodesptitSeb2024-01-271-0/+26
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* [ARM64_DYNAREC][32BITS] Added 37 opcodeptitSeb2024-01-271-1/+13
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* [ARM64_DYNAREC][32BITS] Added 27 opcodeptitSeb2024-01-271-2/+14
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* [ARM64_DYNAREC][32BITS] Added 2F opcodeptitSeb2024-01-271-1/+13
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