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* [ANDOIRD] Fix buildptitSeb2024-04-221-2/+0
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* [TRACE] Fixed some dumpreg when x87stack is incoherentptitSeb2024-04-221-1/+3
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* [ANDROID] Try to fix test 07ptitSeb2024-04-221-0/+7
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* [ARM64_PRINTER] Added SHL printerptitSeb2024-04-221-0/+11
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* [ARM64_PRINTER] Fix some case of DecodeBit not working for 64bits valuesptitSeb2024-04-201-3/+5
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* Added 1 more sdl2 function (for #1458)ptitSeb2024-04-191-0/+1
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* Added 2 wrapped functions to sdl2ptitSeb2024-04-181-0/+2
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* Wrapped 1 more function for mpg123 (#1454)Yang Liu2024-04-171-0/+1
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* Added 66 68 opcode ([ARM64_DYNAREC] too)ptitSeb2024-04-172-0/+10
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* [DYNAREC] Fixed CF flag computation (#1453)Yang Liu2024-04-172-12/+22
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* [RV64_DYNAREC] Added more opcodes (#1451)ZoHan2024-04-171-0/+22
| | | | | * [RV64_DYNAREC] Added more opcodes * modify the format
* [LA64_DYNAREC] Added more opcodes (#1447)Yang Liu2024-04-149-4/+284
| | | | | | | | | | | | | | | | | | | | | * Added B4..B7 MOV opcode * Added 66 81,83 /5 SUB opcode * Added 30 XOR opcode * Added F0 01 LOCK ADD opcode * Added 66 81,83 /0 ADD opcode * Added 66 39 CMP opcode * Added 66 0F D6 MOVQ opcode * Added 0F 57 XORPS opcode * Fix * Added 66 0F 61 opcode
* [LA64_DYNAREC] Added 1 more opcode and some fixes too (#1444)Yang Liu2024-04-145-4/+89
| | | | | | | * Added D3 /0 ROL opcode * Refined emit_sub32c * Fixed BSF and BSR
* [DYNAREC] Fixed shift xw macros (#1443)Yang Liu2024-04-142-14/+47
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* Fixed a few warning here and there...ptitSeb2024-04-1311-249/+217
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* [LA64_DYNAREC] Added more opcodes (#1441)Yang Liu2024-04-125-0/+184
| | | | | | | | | | | | | | | * Added 66 C7 MOV opcode * Added B0..B3 MOV opcode * Added F0 87 LOCK XCHG opcode * Added 35 XOR opcode * Added F7 /7 IDIV opcode * Added BC BSF opcode * Added BD BSR opcode
* Revert some cpuid changes, they are more wrong then right it seemsptitSeb2024-04-121-2/+2
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* [RV64_DYNAREC] Fixed 66 C7 MOV opcode (#1440)Yang Liu2024-04-121-3/+2
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* [LA64_DYNAREC] Added more opcodes and fixed more issues (#1439)Yang Liu2024-04-124-6/+113
| | | | | | | | | | | | | | | | | * Added F3 0F 10 MOVSS opcodes * Added F3 0F 2A CVTSI2SS opcode * Added F3 0F 5E opcode * Added F3 0F 11 MOVSS opcode * Added 0C OR opcode * Added F3 0F 59 MULSS opcode * Added 81,83 /3 SBB opcode * Fixed 2 typos
* [LA64_DYNAREC] Made the CALLRET optimization complete (#1438)Yang Liu2024-04-123-0/+59
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* [RV64_DYNAREC] Implementation of some CRC32 instructions (#1435)kaixindeken2024-04-122-1/+58
| | | | | | | * [RV64_Dynarec] Implementation of some CRC32 instructions * Use BEXTI to detect the lowest bit * Prefer ANDI for lowest bit checking
* [LA64_DYNAREC] Small fix on emit_or32c LBT path (#1436)Yang Liu2024-04-111-1/+4
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* [LA64_DYNAREC] Added more opcodes to the printer (#1433)Yang Liu2024-04-103-429/+1963
| | | | | | | | | | | * Use ROTR * Added more opcodes to the printer * Added even more opcode to the printer * Fixed typos * More
* [LA64_DYNAREC] Refined MOV64 macros (#1430)Yang Liu2024-04-093-28/+48
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* Added 1 more function to icuucXX wrapped libs (for #1428)ptitSeb2024-04-085-0/+5
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* [DYNAREC] Enabled larger dynablockptitSeb2024-04-071-1/+1
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* [ARM64_DYNAREC] Small change to stay in sync with other backendptitSeb2024-04-071-2/+2
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* Fixed 0F A3 BT opcode (#1427)Yang Liu2024-04-072-1/+11
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* [RV64_DYNAREC] Fixed various bugs in shift instructions (#1426)xctan2024-04-074-146/+764
| | | | | | | | | | | | | | | | | | | * [RV64_DYNAREC] Optimized 8-bit constant shifts * [RV64_DYNAREC] Fixed shl8c when c > 8 * [RV64_DYNAREC] Optimized 16-bit constant shifts * [RV64_DYNAREC] Optimized 8-bit CL shifts * [RV64_DYNAREC] Fixed SF generation of 32-bit SHL Ed, CL * [RV64_DYNAREC] Optimized 16-bit CL shifts * [RV64_DYNAREC] Fixed typo in 8-bit CL SHL and SHR * [RV64_DYNAREC] Fixed the wrong mask in 8-bit SHL Eb, CL * [RV64_DYNAREC] Fixed typo in SAR Ew, CL
* [LA64_DYNAREC] Added more opcodes (#1425)Yang Liu2024-04-067-10/+272
| | | | | | | | | | | | | | | | | | | * Added 0B OR opcode * Added D3 /7 SAR opcode * Added D3 /5 SHR opcode * Added 80 /1 OR opcode * Addeded 66 0F BE MOVSX opcode * Fixed SRAxw * Fix * Added 0F C8..CF BSWAP opcode * Added more opcodes
* [LA64_DYNAREC] Added more opcodes (#1424)Yang Liu2024-04-064-2/+260
| | | | | | | | | | | | | * [LA64_DYNAREC] Added 66 C1 /5 SHR opcode * Added 69 IMUL opcode * Added F7 /6 DIV opcode * Added 6B IMUL opcode * Added C1 /1 ROR opcode * [LA64_DYNAREC] Added 87 XCHG opcode
* [LA64_DYNAREC] Added more opcode and fixes (#1423)Yang Liu2024-04-066-7/+117
| | | | | | | | | | | | | * Fixed F2 0F MOVSD opcode * Added F3 0F 6F MOVDQU opcode * Added F2,F3 A5 MOVSD opcode * Added 80 /5 SUB opcode * Fixed a typo in .clang-format * Added 66 85 TEST opcode and a fix
* [LA64_DYNAREC] Added more opcodes (#1422)Yang Liu2024-04-064-4/+202
| | | | | | | | | | | * Added 1C SBB opcode * Added 3A CMP opcode * Added 38 CMP opcode * Added 81,83 /6 XOR opcode * Added F7 /4 MUL opcode
* [LA64_DYNAREC] Added more SSE/SSE2 instructions (#1421)Haichen Wu2024-04-062-0/+50
| | | | | * [LA64_DYNAREC] Added more SSE/SSE2 instructions * [LA64_DYNAREC] Added more SSE/SSE2 instructions
* [LA64_DYNAREC] Fixed missing LBT path and more (#1419)Yang Liu2024-04-063-16/+25
| | | | | | | * [LA64_DYNAREC] Fixed missing LBT path and more * Fixed D3 /4/6 SHL opcode * LA64 qemu is not stable too
* [DYNAREC] Fixed REP opcodes for correct register state recovery (#1420)Yang Liu2024-04-063-9/+9
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* [LA64_DYNAREC] Added more opcodes (#1418)Yang Liu2024-04-055-2/+205
| | | | | | | | | | | * Added 0F A3 BT opcode * Added 3C CMP opcode * Added C0 /4/5/6/7 opcodes * Added 6A PUSH opcode * Added F2,F3 A6 CMPSB opcode
* [LA64_DYNAREC] Added more opcodes (#1417)Yang Liu2024-04-056-2/+265
| | | | | | | | | * Added 64 8B MOV opcode * Added 64 33 XOR opcode * Added 19 SBB opcode * Smol fix
* [LA64_DYNAREC] Added more opcodes (#1416)Yang Liu2024-04-057-3/+295
| | | | | | | | | * [LA64_DYNAREC] Added 0F AF IMUL opcode * Update clang-format rules * Added 08 OR opcode * Added F7 /3 NEG opcode and fixed some potential bugs
* [LA64_DYNAREC] Fixed SSE issues (#1415)Yang Liu2024-04-052-15/+18
| | | | | * [LA64_DYNAREC] Fixed SSE issues * Fixed MOVSD modreg
* [LA64_DYNAREC] Added more SSE/SSE2 instructions (#1410)Haichen Wu2024-04-045-0/+149
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* Wrapped some more functions to gstreamer-1.0 and friends (for #1397)ptitSeb2024-04-036-6/+66
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* Wrapped 2 more functionto gstreamer-1.0 (for #1397)ptitSeb2024-04-034-2/+32
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* Wrapped GstAudioFilter (for #1397)ptitSeb2024-04-033-1/+69
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* [RCFILE] Make sure strdup is coherent with freeptitSeb2024-04-031-4/+4
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* [INTERPRETER] Added aligned path to F0 0F C7 opcodeptitSeb2024-04-031-0/+37
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* [RV64_DYNAREC] Added 0F 70 PSHUFW opcode (#1408)Yang Liu2024-04-031-0/+15
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* [RV64_DYNAREC] Add 1E/1F opcode (#1407)ZoHan2024-04-031-4/+27
| | | | | | | * [RV64_DYNAREC] Add 1E/1F opcode * modify the format * modify the format
* [RV64_DYNAREC] Add more opcodes (#1405)ZoHan2024-04-031-0/+36
| | | | | * [RV64_DYNAREC] Add more opcodes * modify the format
* [ARM64_DYNAREC] Better fix for #1366, that should help #1383)ptitSeb2024-04-024-6/+5
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