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authorPeter Maydell <peter.maydell@linaro.org>2016-06-27 11:48:21 +0100
committerPeter Maydell <peter.maydell@linaro.org>2016-06-27 11:48:22 +0100
commit4b86bac21c15cd04cf333423c8c256e4dc4dc925 (patch)
tree22492178fd48b0302a06c694deb1417544454b26 /hw/intc/arm_gicv3_cpuif.c
parent929bf947f7cc928e052a7cbd538227710e68e42e (diff)
parent77be419980114d75605811e1681115d0919cfa1a (diff)
downloadfocaccia-qemu-4b86bac21c15cd04cf333423c8c256e4dc4dc925.tar.gz
focaccia-qemu-4b86bac21c15cd04cf333423c8c256e4dc4dc925.zip
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160624' into staging
MIPS patches 2016-06-24

Changes:
* support IEEE 754-2008 in MIPS CPUs

# gpg: Signature made Fri 24 Jun 2016 16:09:38 BST
# gpg:                using RSA key 0x52118E3C0B29DA6B
# gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>"
# Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4  4FC0 5211 8E3C 0B29 DA6B

* remotes/lalrae/tags/mips-20160624:
  target-mips: Add FCR31's FS bit definition
  target-mips: Implement FCR31's R/W bitmask and related functionalities
  target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>
  target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>
  target-mips: Activate IEEE 754-2008 signaling NaN bit meaning for MSA
  linux-user: Update preprocessor constants for Mips-specific e_flags bits
  softfloat: Handle snan_bit_is_one == 0 in MIPS pickNaNMulAdd()
  softfloat: For Mips only, correct default NaN values
  softfloat: Clean code format in fpu/softfloat-specialize.h
  softfloat: Implement run-time-configurable meaning of signaling NaN bit

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/arm_gicv3_cpuif.c')
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