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path: root/accel/tcg/cputlb.c (follow)
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* accel/tcg/cputlb.c: Widen addr in MMULookupPageDataAnton Johansson2023-06-261-15/+15
* accel/tcg/cputlb.c: Widen CPUTLBEntry access functionsAnton Johansson2023-06-261-4/+4
* accel: Replace target_ulong in tlb_*()Anton Johansson2023-06-261-90/+87
* accel/tcg: Handle MO_ATOM_WITHIN16 in do_st16_leNRichard Henderson2023-06-201-0/+1
* tcg: Split helper-proto.hRichard Henderson2023-06-051-2/+1
* tcg: Split out tcg/oversized-guest.hRichard Henderson2023-06-051-0/+1
* tcg: Widen CPUTLBEntry comparators to 64-bitsRichard Henderson2023-06-051-2/+6
* accel/tcg: Correctly use atomic128.h in ldst_atomicity.c.incRichard Henderson2023-05-231-1/+1
* accel/tcg: Eliminate #if on HAVE_ATOMIC128 and HAVE_CMPXCHG128Richard Henderson2023-05-231-1/+1
* accel/tcg: Remove prot argument to atomic_mmu_lookupRichard Henderson2023-05-231-53/+30
* accel/tcg: Unify cpu_{ld,st}*_{be,le}_mmuRichard Henderson2023-05-231-99/+23
* tcg: Widen helper_{ld,st}_i128 addresses to uint64_tRichard Henderson2023-05-161-3/+2
* accel/tcg: Widen tcg-ldst.h addresses to uint64_tRichard Henderson2023-05-161-13/+13
* tcg: Add 128-bit guest memory primitivesRichard Henderson2023-05-161-94/+305
* tcg: Unify helper_{be,le}_{ld,st}*Richard Henderson2023-05-161-129/+61
* accel/tcg: Honor atomicity of storesRichard Henderson2023-05-161-60/+48
* accel/tcg: Honor atomicity of loadsRichard Henderson2023-05-161-39/+136
* accel/tcg: Reorg system mode store helpersRichard Henderson2023-05-111-208/+186
* accel/tcg: Reorg system mode load helpersRichard Henderson2023-05-111-209/+412
* accel/tcg: Introduce tlb_read_idxRichard Henderson2023-05-111-71/+33
* accel/tcg: Fix atomic_mmu_lookup for readsRichard Henderson2023-05-111-1/+1
* tcg: Widen helper_*_st[bw]_mmu val argumentsRichard Henderson2023-05-051-3/+3
* accel/tcg: Add cpu_ld*_code_mmuRichard Henderson2023-05-021-0/+48
* accel/tcg: Uncache the host address for instruction fetch when tlb size < 1Weiwei Li2023-05-021-0/+5
* accel/tcg: Trigger watchpoints from atomic_mmu_lookupRichard Henderson2023-03-051-11/+29
* accel/tcg: Honor TLB_DISCARD_WRITE in atomic_mmu_lookupRichard Henderson2023-03-051-1/+1
* accel/tcg: Retain prot flags from tlb_fillRichard Henderson2023-03-051-1/+0
* accel/tcg: Add 'size' param to probe_access_fullRichard Henderson2023-02-281-2/+2
* accel/tcg: Add 'size' param to probe_access_flags()Daniel Henrique Barboza2023-02-281-3/+14
* tcg: Add guest load/store primitives for TCGv_i128Richard Henderson2023-02-041-0/+112
* accel/tcg: Test CPUJumpCache in tb_jmp_cache_clear_pageEric Auger2023-02-041-1/+6
* bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plxPhilippe Mathieu-Daudé2023-01-181-1/+1
* accel/tcg: Use QEMU_IOTHREAD_LOCK_GUARD in io_readx/io_writexRichard Henderson2023-01-041-17/+8
* accel/tcg: Factor tb_invalidate_phys_range_fast() outPhilippe Mathieu-Daudé2022-12-201-4/+1
* accel/tcg: Rename tb_invalidate_phys_page_fast{,__locked}()Philippe Mathieu-Daudé2022-12-201-1/+1
* accel/tcg: Remove trace events from trace-root.hPhilippe Mathieu-Daudé2022-12-201-1/+1
* include/hw/core: Create struct CPUJumpCacheRichard Henderson2022-10-041-4/+5
* accel/tcg: Inline tb_flush_jmp_cacheRichard Henderson2022-10-041-11/+14
* accel/tcg: Do not align tb->page_addr[0]Richard Henderson2022-10-041-1/+2
* accel/tcg: Introduce tlb_set_page_fullRichard Henderson2022-10-031-18/+33
* accel/tcg: Introduce probe_access_fullRichard Henderson2022-10-031-18/+29
* accel/tcg: Suppress auto-invalidate in probe_access_internalRichard Henderson2022-10-031-1/+9
* accel/tcg: Drop addr member from SavedIOTLBRichard Henderson2022-10-031-4/+3
* accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFullRichard Henderson2022-10-031-50/+52
* cputlb: used cached CPUClass in our hot-pathsAlex Bennée2022-10-031-9/+6
* accel/tcg: Use probe_access_internal for softmmu get_page_addr_code_hostpRichard Henderson2022-09-061-50/+26
* accel/tcg: Move qemu_ram_addr_from_host_nofail to physmem.cRichard Henderson2022-09-061-12/+0
* accel/tcg: Properly implement get_page_addr_code for user-onlyRichard Henderson2022-09-061-5/+0
* accel/tcg: Fix unaligned stores to s390x low-address-protected lowcoreIlya Leoshkevich2022-07-121-3/+5
* accel/tcg: Assert mmu_idx in range before use in cputlbRichard Henderson2022-04-261-13/+27