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path: root/hw/riscv/sifive_u.c (follow)
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* qom: Have class_init() take a const data argumentPhilippe Mathieu-Daudé2025-04-251-2/+2
* hw/boards: Rename no_sdcard -> auto_create_sdcardPhilippe Mathieu-Daudé2025-02-161-1/+1
* hw/boards: Explicit no_sdcard=false as ON_OFF_AUTO_OFFPhilippe Mathieu-Daudé2025-02-161-0/+1
* Merge tag 'exec-20241220' of https://github.com/philmd/qemu into stagingStefan Hajnoczi2024-12-211-3/+3
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| * include: Rename sysemu/ -> system/Philippe Mathieu-Daudé2024-12-201-3/+3
* | Merge tag 'pull-riscv-to-apply-20241220' of https://github.com/alistair23/qem...Stefan Hajnoczi2024-12-211-7/+11
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| * | hw/riscv: Add a new struct RISCVBootInfoJim Shu2024-12-201-5/+7
| * | hw/riscv: Support to load DTB after 3GB memory on 64-bit system.Jim Shu2024-12-201-3/+5
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* / include/hw/qdev-properties: Remove DEFINE_PROP_END_OF_LISTRichard Henderson2024-12-191-1/+0
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* hw/riscv: Constify all PropertyRichard Henderson2024-12-151-1/+1
* target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBITANG Tiancheng2024-10-301-1/+2
* Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell2024-10-041-1/+0
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| * hw: Remove unused inclusion of hw/char/serial.hBernhard Beschow2024-10-031-1/+0
* | hw/riscv: Respect firmware ELF entry pointSamuel Holland2024-10-021-2/+2
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* target/riscv: support new isa extension detection devicetree propertiesConor Dooley2024-02-091-5/+2
* hw/riscv: use qemu_configure_nic_device()David Woodhouse2024-02-021-6/+1
* hw/sd: Introduce a "sd-card" SPI variant modelCédric Le Goater2023-09-011-2/+1
* hw/riscv: Move the dtb load bits outside of create_fdt()Bin Meng2023-03-011-16/+15
* hw/riscv: Skip re-generating DT nodes for a given DTBBin Meng2023-03-011-0/+1
* hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()Daniel Henrique Barboza2023-02-161-10/+1
* hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel()Daniel Henrique Barboza2023-02-161-1/+2
* hw/riscv: change riscv_compute_fdt_addr() semanticsDaniel Henrique Barboza2023-02-071-1/+2
* hw/riscv: split fdt address calculation from fdt loadDaniel Henrique Barboza2023-02-071-3/+4
* hw/riscv/sifive_u.c: simplify create_fdt()Daniel Henrique Barboza2023-01-201-4/+4
* hw/riscv/boot.c: use MachineState in riscv_load_kernel()Daniel Henrique Barboza2023-01-201-2/+1
* hw/riscv/boot.c: use MachineState in riscv_load_initrd()Daniel Henrique Barboza2023-01-201-2/+1
* hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel()Daniel Henrique Barboza2023-01-201-6/+5
* hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()Daniel Henrique Barboza2023-01-201-8/+2
* hw/riscv/sifive_u: use 'fdt' from MachineStateDaniel Henrique Barboza2023-01-201-9/+6
* hw/riscv/boot.c: introduce riscv_default_firmware_name()Daniel Henrique Barboza2023-01-201-7/+4
* hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"Bin Meng2023-01-061-1/+2
* hw/riscv: set machine->fdt in sifive_u_machine_init()Daniel Henrique Barboza2022-10-171-0/+3
* hw/riscv/sifive_u: Resolve redundant property accessorsBernhard Beschow2022-05-241-20/+4
* hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)Tsukasa OI2022-05-241-2/+2
* hw/riscv: Don't add empty bootargs to device treeBin Meng2022-04-291-1/+1
* hw/riscv: Use error_fatal for SoC realisationAlistair Francis2022-01-081-1/+1
* hw: Replace trivial drive_get_next() by drive_get()Markus Armbruster2021-12-151-1/+1
* hw/sd/ssi-sd: Do not create SD card within controller's realizeMarkus Armbruster2021-12-151-1/+12
* hw/riscv: sifive_u: Use the PLIC config helper functionAlistair Francis2021-10-281-13/+1
* hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_idBin Meng2021-10-221-4/+2
* hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel2021-09-211-3/+6
* hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel2021-09-211-1/+1
* sifive_u: Connect the SiFive PWM deviceAlistair Francis2021-09-211-1/+54
* hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis2021-09-211-1/+1
* arch_init.h: Don't include arch_init.h unnecessarilyPeter Maydell2021-08-261-1/+0
* hw/riscv: sifive_u: Make sure firmware info is 8-byte alignedBin Meng2021-07-151-2/+3
* hw/riscv: sifive_u: Correct the CLINT timebase frequencyBin Meng2021-07-151-2/+5
* hw/riscv: Use macros for BIOS image namesBin Meng2021-06-081-4/+2
* hw/riscv: Support the official PLIC DT bindingsBin Meng2021-06-081-1/+5
* hw/riscv: Support the official CLINT DT bindingsBin Meng2021-06-081-1/+5