summary refs log tree commit diff stats
path: root/include/hw/riscv/microchip_pfsoc.h (follow)
Commit message (Collapse)AuthorAgeFilesLines
* hw/riscv: Configurable MPFS CLINT timebase freqSebastian Huber2025-05-191-0/+1
| | | | | | | | | | | | | This property enables the setting of the CLINT timebase frequency through the command line, for example: -machine microchip-icicle-kit,clint-timebase-frequency=10000000 Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250319061342.26435-6-sebastian.huber@embedded-brains.de> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* include: Include headers where neededMarkus Armbruster2023-01-081-0/+3
| | | | | | | | | | | | A number of headers neglect to include everything they need. They compile only if the headers they need are already included from elsewhere. Fix that. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221222120813.727830-3-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0Bin Meng2023-01-061-1/+1
| | | | | | | | | | | | | | | | | | | | At present the SiFive PLIC model "priority-base" expects interrupt priority register base starting from source 1 instead source 0, that's why on most platforms "priority-base" is set to 0x04 except 'opentitan' machine. 'opentitan' should have set "priority-base" to 0x04 too. Note the irq number calculation in sifive_plic_{read,write} is correct as the codes make up for the irq number by adding 1. Let's simply update "priority-base" to start from interrupt source 0 and add a comment to make it crystal clear. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Message-Id: <20221211030829.802437-14-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLICBin Meng2023-01-061-1/+1
| | | | | | | | | | | | | | | | Per chapter 6.5.2 in [1], the number of interupt sources including interrupt source 0 should be 187. [1] PolarFire SoC MSS TRM: https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/ReferenceManuals/PolarFire_SoC_FPGA_MSS_Technical_Reference_Manual_VC.pdf Fixes: 56f6e31e7b7e ("hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board") Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Message-Id: <20221211030829.802437-10-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/{misc, riscv}: pfsoc: add system controller as unimplementedConor Dooley2023-01-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | The system controller on PolarFire SoC is access via a mailbox. The control registers for this mailbox lie in the "IOSCB" region & the interrupt is cleared via write to the "SYSREG" region. It also has a QSPI controller, usually connected to a flash chip, that is used for storing FPGA bitstreams and used for In-Application Programming (IAP). Linux has an implementation of the system controller, through which the hwrng is accessed, leading to load/store access faults. Add the QSPI as unimplemented and a very basic (effectively unimplemented) version of the system controller's mailbox. Rather than purely marking the regions as unimplemented, service the mailbox requests by reporting failures and raising the interrupt so a guest can better handle the lack of support. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221117225518.4102575-4-conor@kernel.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: pfsoc: add missing FICs as unimplementedConor Dooley2023-01-061-0/+2
| | | | | | | | | | | | | | | | | | The Fabric Interconnect Controllers provide interfaces between the FPGA fabric and the core complex. There are 5 FICs on PolarFire SoC, numbered 0 through 4. FIC2 is an AXI4 slave interface from the FPGA fabric and does not show up on the MSS memory map. FIC4 is dedicated to the User Crypto Processor and does not show up on the MSS memory map either. FIC 0, 1 & 3 do show up in the MSS memory map and neither FICs 0 or 1 are represented in QEMU, leading to load access violations while booting Linux for Icicle if PCIe is enabled as the root port is connected via either FIC 0 or 1. Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Message-Id: <20221117225518.4102575-3-conor@kernel.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripheralsConor Dooley2022-09-071-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Booting using "Direct Kernel Boot" for PolarFire SoC & skipping u-boot entirely is probably not advisable, but it does at least show signs of life. Recent Linux kernel versions make use of peripherals that are missing definitions in QEMU and lead to kernel panics. These issues almost certain rear their head for other methods of booting, but I was unable to figure out a suitable HSS version that is recent enough to support these peripherals & works with QEMU. With these peripherals added, booting a kernel with the following hangs hangs waiting for the system controller's hwrng, but the kernel no longer panics. With the Linux driver for hwrng disabled, it boots to console. qemu-system-riscv64 -M microchip-icicle-kit \ -m 2G -smp 5 \ -kernel $(vmlinux_bin) \ -dtb $(dtb)\ -initrd $(initramfs) \ -display none -serial null \ -serial stdio More peripherals are added than strictly required to fix the panics in the hopes of avoiding a replication of this problem in the future. Some of the peripherals which are in the device tree for recent kernels are implemented in the FPGA fabric. The eMMC/SD mux, which exists as an unimplemented device is replaced by a wider entry. This updated entry covers both the mux & the remainder of the FPGA fabric connected to the MSS using Fabric Interrconnect (FIC) 3. Link: https://github.com/polarfire-soc/icicle-kit-reference-design#fabric-memory-map Link: https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/SupportingCollateral/V1_4_Register_Map.zip Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220813135127.2971754-1-mail@conchuod.ie> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: microchip_pfsoc: Use the PLIC config helper functionAlistair Francis2021-10-281-1/+0
| | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20211022060133.3045020-4-alistair.francis@opensource.wdc.com
* hw/riscv: microchip_pfsoc: Map EMMC/SD mux registerBin Meng2021-03-221-0/+1
| | | | | | | | | | | | | | | | | Since HSS commit c20a89f8dcac, the Icicle Kit reference design has been updated to use a register mapped at 0x4f000000 instead of a GPIO to control whether eMMC or SD card is to be used. With this support the same HSS image can be used for both eMMC and SD card boot flow, while previously two different board configurations were used. This is undocumented but one can take a look at the HSS code HSS_MMCInit() in services/mmc/mmc_api.c. With this commit, HSS image built from 2020.12 release boots again. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: microchip_pfsoc: add QSPI NOR flashVitaly Wool2020-12-171-0/+3
| | | | | | | | | | Add QSPI NOR flash definition for Microchip PolarFire SoC. Signed-off-by: Vitaly Wool <vitaly.wool@konsulko.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Message-id: 20201112074950.33283-1-vitaly.wool@konsulko.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: microchip_pfsoc: Hook the I2C1 controllerBin Meng2020-11-031-0/+1
| | | | | | | | | | | | | | | | | The latest SD card image [1] released by Microchip ships a Linux kernel with built-in PolarFire SoC I2C driver support. The device tree file includes the description for the I2C1 node hence kernel tries to probe the I2C1 device during boot. It is enough to create an unimplemented device for I2C1 to allow the kernel to continue booting to the shell. [1] ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1603863010-15807-11-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: microchip_pfsoc: Correct DDR memory mapBin Meng2020-11-031-1/+4
| | | | | | | | | | | | | | | | | | | | | When system memory is larger than 1 GiB (high memory), PolarFire SoC maps it at address 0x10_0000_0000. Address 0xC000_0000 and above is aliased to the same 1 GiB low memory with different cache attributes. At present QEMU maps the system memory contiguously from 0x8000_0000. This corrects the wrong QEMU logic. Note address 0x14_0000_0000 is the alias to the high memory, and even physical memory is only 1 GiB, the HSS codes still tries to probe the high memory alias address. It seems there is no issue on the real hardware, so we will have to take that into the consideration in our emulation. Due to this, we we increase the default system memory size to 1537 MiB (the minimum required high memory size by HSS) so that user gets notified an error when less than 1537 MiB is specified. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201101170538.3732-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: microchip_pfsoc: Map the reserved memory at address 0Bin Meng2020-11-031-0/+1
| | | | | | | | | | | | | Somehow HSS needs to access address 0 [1] for the DDR calibration data which is in the chipset's reserved memory. Let's map it. [1] See the config_copy() calls in various places in ddr_setup() in the HSS source codes. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1603863010-15807-9-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: microchip_pfsoc: Connect the SYSREG moduleBin Meng2020-11-031-0/+2
| | | | | | | | | | Previously SYSREG was created as an unimplemented device. Now that we have a simple SYSREG module, connect it. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1603863010-15807-8-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: microchip_pfsoc: Connect the IOSCB moduleBin Meng2020-11-031-1/+3
| | | | | | | | | | | | Previously IOSCB_CFG was created as an unimplemented device. With the new IOSCB model, its memory range is already covered by the IOSCB hence remove the previous unimplemented device creation in the SoC codes. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1603863010-15807-6-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: microchip_pfsoc: Connect DDR memory controller modulesBin Meng2020-11-031-0/+5
| | | | | | | | | Connect DDR SGMII PHY module and CFG module to the PolarFire SoC. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1603863010-15807-4-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: microchip_pfsoc: Hook GPIO controllersBin Meng2020-09-091-0/+3
| | | | | | | | | | | | | | | | | | | | Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems enough to create unimplemented devices to cover their register spaces at this point. With this commit, QEMU can boot to U-Boot (2nd stage bootloader) all the way to the Linux shell login prompt, with a modified HSS (1st stage bootloader). For detailed instructions on how to create images for the Icicle Kit board, please check QEMU RISC-V WiKi page at: https://wiki.qemu.org/Documentation/Platforms/RISCV Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-15-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng2020-09-091-0/+7
| | | | | | | | | | | | | | | | | | Microchip PolarFire SoC integrates 2 Candence GEMs to provide IEEE 802.3 standard-compliant 10/100/1000 Mbps ethernet interface. On the Icicle Kit board, GEM0 connects to a PHY at address 8 while GEM1 connects to a PHY at address 9. The 2nd stage bootloader (U-Boot) is using GEM1 by default, so we must specify 2 '-nic' options from the command line in order to get a working ethernet. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-14-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng2020-09-091-0/+11
| | | | | | | | | | | On the Icicle Kit board, the HSS firmware utilizes the on-chip DMA controller to move the 2nd stage bootloader in the system memory. Let's connect a DMA controller to Microchip PolarFire SoC. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-11-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng2020-09-091-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Microchip PolarFire SoC integrates one Cadence SDHCI controller. On the Icicle Kit board, one eMMC chip and an external SD card connect to this controller depending on different configuration. As QEMU does not support eMMC yet, we just emulate the SD card configuration. To test this, the Hart Software Services (HSS) should choose the SD card configuration: $ cp boards/icicle-kit-es/def_config.sdcard .config $ make BOARD=icicle-kit-es The SD card image can be built from the Yocto BSP at: https://github.com/polarfire-soc/meta-polarfire-soc-yocto-bsp Note the generated SD card image should be resized before use: $ qemu-img resize /path/to/sdcard.img 4G Launch QEMU with the following command: $ qemu-system-riscv64 -nographic -M microchip-icicle-kit -sd sdcard.img Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-9-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng2020-09-091-0/+20
| | | | | | | | | | Microchip PolarFire SoC has 5 MMUARTs, and the Icicle Kit board wires 4 of them out. Let's connect all 5 MMUARTs. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-7-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng2020-09-091-0/+88
This is an initial support for Microchip PolarFire SoC Icicle Kit. The Icicle Kit board integrates a PolarFire SoC, with one SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA. For more details about Microchip PolarFire Soc, please see: https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000. The following perepherals are created as an unimplemented device: - Bus Error Uint 0/1/2/3/4 - L2 cache controller - SYSREG - MPUCFG - IOSCBCFG More devices will be added later. The BIOS image used by this machine is hss.bin, aka Hart Software Services, which can be built from: https://github.com/polarfire-soc/hart-software-services To launch this machine: $ qemu-system-riscv64 -nographic -M microchip-icicle-kit The memory is set to 1 GiB by default to match the hardware. A sanity check on ram size is performed in the machine init routine to prompt user to increase the RAM size to > 1 GiB when less than 1 GiB ram is detected. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-5-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>