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path: root/include/hw/riscv/virt.h (follow)
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* hw/riscv/virt.h: correct typosManos Pitsidianakis2024-02-211-2/+2
* hw/riscv/virt: Update GPEX MMIO related propertiesSunil V L2024-01-101-0/+1
* hw/riscv: virt: Make few IMSIC macros and functions publicSunil V L2024-01-101-0/+25
* hw/riscv/virt: Enable basic ACPI infrastructureSunil V L2023-03-061-0/+1
* hw/riscv/virt: Add memmap pointer to RiscVVirtStateSunil V L2023-03-061-0/+1
* hw/riscv/virt: Add a switch to disable ACPISunil V L2023-03-061-0/+2
* hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fieldsSunil V L2023-03-061-0/+2
* include: Include headers where neededMarkus Armbruster2023-01-081-1/+1
* hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0Bin Meng2023-01-061-1/+1
* hw/riscv: virt: Fix the value of "riscv, ndev" in the dtbBin Meng2023-01-061-3/+2
* hw/riscv: virt: Remove the redundant ipi-id propertyAtish Patra2023-01-061-1/+0
* hw/riscv: virt: fix the plic's address cellsConor Dooley2022-09-071-0/+1
* hw/riscv: virt: Create a platform busAlistair Francis2022-04-291-1/+6
* hw/riscv: virt: Add a machine done notifierAlistair Francis2022-04-291-0/+1
* hw/riscv: virt: Increase maximum number of allowed CPUsAnup Patel2022-03-031-1/+1
* hw/riscv: virt: Add optional AIA IMSIC support to virt machineAnup Patel2022-03-031-3/+14
* hw/riscv: virt: Add optional AIA APLIC support to virt machineAnup Patel2022-03-031-6/+20
* hw/riscv: virt: Allow support for 32 coresAlistair Francis2022-01-081-1/+1
* hw/riscv: virt: Don't use a macro for the PLIC configurationAlistair Francis2021-10-281-1/+0
* hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel2021-09-211-0/+2
* hw/riscv: Add fw_cfg support to virtAsherah Connor2021-03-221-0/+2
* hw/riscv: migrate fdt field to generic MachineStateAlex Bennée2021-03-101-1/+0
* riscv: virt: Remove target macro conditionalsAlistair Francis2020-12-171-6/+0
* Use DECLARE_*CHECKER* macrosEduardo Habkost2020-09-091-2/+2
* Move QOM typedefs and add missing includesEduardo Habkost2020-09-091-2/+4
* hw/riscv: virt: Allow creating multiple NUMA socketsAnup Patel2020-08-251-2/+7
* riscv: virt: Use Goldfish RTC deviceAnup Patel2020-02-101-0/+2
* riscv/virt: Add the PFlash CFI01 deviceAlistair Francis2019-10-281-0/+3
* riscv/virt: Manually define the machineAlistair Francis2019-10-281-1/+6
* riscv: hw: Drop "clock-frequency" property of cpu nodesBin Meng2019-10-281-4/+0
* include: Make headers more self-containedMarkus Armbruster2019-08-161-0/+3
* target/riscv: Add a base 32 and 64 bit CPUAlistair Francis2019-05-241-2/+2
* riscv: plic: Fix incorrect irq calculationAlistair Francis2019-04-041-1/+1
* hw/riscv/virt: Connect the gpex PCIeAlistair Francis2018-12-201-1/+12
* hw/riscv/virt: Increase the number of interruptsAlistair Francis2018-12-201-1/+1
* RISC-V: Make virt header comment title consistentMichael Clark2018-05-061-1/+1
* RISC-V: Make some header guards more specificMichael Clark2018-05-061-2/+2
* RISC-V: Remove unused class definitionsMichael Clark2018-05-061-5/+0
* RISC-V: Use ROM base address and size from memmapMichael Clark2018-05-061-2/+0
* RISC-V: Replace hardcoded constants with enum valuesMichael Clark2018-05-061-0/+4
* RISC-V VirtIO MachineMichael Clark2018-03-071-0/+74