| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | target/arm: Refactor default generic timer frequency handling | Peter Maydell | 2024-04-30 | 1 | -8/+8 |
| * | target/arm: Implement ID_AA64MMFR3_EL1 | Peter Maydell | 2024-04-30 | 1 | -2/+4 |
| * | target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64() | Jinjie Ruan | 2024-04-25 | 1 | -0/+3 |
| * | target/arm: Handle PSTATE.ALLINT on taking an exception | Jinjie Ruan | 2024-04-25 | 1 | -0/+8 |
| * | target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMI | Jinjie Ruan | 2024-04-25 | 1 | -0/+13 |
| * | target/arm: Add support for NMI in arm_phys_excp_target_el() | Jinjie Ruan | 2024-04-25 | 1 | -0/+1 |
| * | target/arm: Add support for Non-maskable Interrupt | Jinjie Ruan | 2024-04-25 | 1 | -4/+29 |
| * | target/arm: Support MSR access to ALLINT | Jinjie Ruan | 2024-04-25 | 1 | -0/+35 |
| * | target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI | Jinjie Ruan | 2024-04-25 | 1 | -1/+7 |
| * | target/arm: Use correct SecuritySpace for AArch64 AT ops at EL3 | Peter Maydell | 2024-04-08 | 1 | -2/+5 |
| * | target/arm: Fix CNTPOFF_EL2 trap to missing EL3 | Pierre-Clément Tosi | 2024-04-05 | 1 | -1/+2 |
| * | target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling | Peter Maydell | 2024-03-07 | 1 | -2/+66 |
| * | target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0 | Peter Maydell | 2024-03-07 | 1 | -0/+43 |
| * | target/arm: Implement new FEAT_ECV trap bits | Peter Maydell | 2024-03-07 | 1 | -5/+46 |
| * | target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written | Peter Maydell | 2024-03-07 | 1 | -0/+18 |
| * | target/arm: use FIELD macro for CNTHCTL bit definitions | Peter Maydell | 2024-03-07 | 1 | -5/+4 |
| * | target/arm: Timer _EL02 registers UNDEF for E2H == 0 | Peter Maydell | 2024-03-07 | 1 | -1/+1 |
| * | target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs | Peter Maydell | 2024-02-15 | 1 | -1/+1 |
| * | target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_F... | Peter Maydell | 2024-02-15 | 1 | -2/+10 |
| * | Merge tag 'pull-tcg-20240202-2' of https://gitlab.com/rth7680/qemu into staging | Peter Maydell | 2024-02-03 | 1 | -1/+1 |
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| | * | target/arm: Split out arm_env_mmu_index | Richard Henderson | 2024-02-03 | 1 | -1/+1 |
| * | | target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set | Peter Maydell | 2024-02-02 | 1 | -0/+1 |
| * | | target/arm: fix exception syndrome for AArch32 bkpt insn | Jan Klötzke | 2024-02-02 | 1 | -0/+18 |
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| * | target/arm: Move GTimer definitions to new 'gtimer.h' header | Philippe Mathieu-Daudé | 2024-01-26 | 1 | -0/+1 |
| * | target/arm: Move e2h_access() helper around | Philippe Mathieu-Daudé | 2024-01-26 | 1 | -14/+15 |
| * | target/arm: Ensure icount is enabled when emulating INST_RETIRED | Philippe Mathieu-Daudé | 2024-01-19 | 1 | -0/+2 |
| * | system/cpu-timers: Introduce ICountMode enumerator | Philippe Mathieu-Daudé | 2024-01-19 | 1 | -1/+2 |
| * | target/arm: Enhance CPU_LOG_INT to show SPSR on AArch64 exception-entry | Peter Maydell | 2024-01-09 | 1 | -0/+1 |
| * | target/arm: Mark up VNCR offsets (offsets >= 0x200, except GIC) | Peter Maydell | 2024-01-09 | 1 | -0/+8 |
| * | target/arm: Mark up VNCR offsets (offsets 0x168..0x1f8) | Peter Maydell | 2024-01-09 | 1 | -0/+18 |
| * | target/arm: Mark up VNCR offsets (offsets 0x100..0x160) | Peter Maydell | 2024-01-09 | 1 | -0/+22 |
| * | target/arm: Mark up VNCR offsets (offsets 0x0..0xff) | Peter Maydell | 2024-01-09 | 1 | -0/+12 |
| * | target/arm: Handle FEAT_NV2 redirection of SPSR_EL2, ELR_EL2, ESR_EL2, FAR_EL2 | Peter Maydell | 2024-01-09 | 1 | -4/+9 |
| * | target/arm: Handle FEAT_NV2 changes to when SPSR_EL1.M reports EL2 | Peter Maydell | 2024-01-09 | 1 | -4/+12 |
| * | target/arm: Implement VNCR_EL2 register | Peter Maydell | 2024-01-09 | 1 | -0/+26 |
| * | target/arm: Handle HCR_EL2 accesses for FEAT_NV2 bits | Peter Maydell | 2024-01-09 | 1 | -0/+3 |
| * | target/arm: Don't honour PSTATE.PAN when HCR_EL2.{NV, NV1} == {1, 1} | Peter Maydell | 2024-01-09 | 1 | -0/+3 |
| * | target/arm: Always use arm_pan_enabled() when checking if PAN is enabled | Peter Maydell | 2024-01-09 | 1 | -11/+11 |
| * | target/arm: Trap registers when HCR_EL2.{NV, NV1} == {1, 1} | Peter Maydell | 2024-01-09 | 1 | -4/+41 |
| * | target/arm: Set SPSR_EL1.M correctly when nested virt is enabled | Peter Maydell | 2024-01-09 | 1 | -0/+6 |
| * | target/arm: Make EL2 cpreg accessfns safe for FEAT_NV EL1 accesses | Peter Maydell | 2024-01-09 | 1 | -7/+58 |
| * | target/arm: *_EL12 registers should UNDEF when HCR_EL2.E2H is 0 | Peter Maydell | 2024-01-09 | 1 | -0/+16 |
| * | target/arm: Record correct opcode fields in cpreg for E2H aliases | Peter Maydell | 2024-01-09 | 1 | -0/+35 |
| * | target/arm: Implement HCR_EL2.AT handling | Peter Maydell | 2024-01-09 | 1 | -6/+15 |
| * | target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NV | Peter Maydell | 2024-01-09 | 1 | -1/+5 |
| * | Replace "iothread lock" with "BQL" in comments | Stefan Hajnoczi | 2024-01-08 | 1 | -1/+1 |
| * | system/cpus: rename qemu_mutex_lock_iothread() to bql_lock() | Stefan Hajnoczi | 2024-01-08 | 1 | -2/+2 |
| * | target/arm: Use generic cpu_list() | Gavin Shan | 2024-01-05 | 1 | -46/+0 |
| * | target/arm/helper: Propagate MDCR_EL2.HPMN into PMCR_EL0.N | Jean-Philippe Brucker | 2023-12-19 | 1 | -2/+20 |
| * | target/arm: Restrict DC CVAP & DC CVADP instructions to TCG accel | Philippe Mathieu-Daudé | 2023-12-19 | 1 | -0/+5 |