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path: root/target/riscv/debug.c (follow)
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* target/riscv: Implement optional CSR mcontext of debug Sdtrig extensionAlvin Chang2024-02-091-0/+2
* target/riscv: Allocate itrigger timers only onceAkihiko Odaki2023-09-111-3/+12
* riscv: spelling fixesMichael Tokarev2023-09-081-5/+5
* target/riscv: Fix lines with over 80 charactersWeiwei Li2023-05-051-5/+6
* target/riscv: Remove riscv_cpu_virt_enabled()Weiwei Li2023-05-051-5/+5
* target/riscv: set tval for triggered watchpointsSergey Matyukevich2023-02-071-1/+0
* target/riscv: Add itrigger_enabled field to CPURISCVStateLIU Zhiwei2023-01-061-0/+3
* target/riscv: Enable native debug itriggerLIU Zhiwei2023-01-061-0/+72
* target/riscv: Add itrigger support when icount is enabledLIU Zhiwei2023-01-061-0/+59
* target/riscv: Add itrigger support when icount is not enabledLIU Zhiwei2023-01-061-0/+71
* cleanup: Tweak and re-run return_directly.cocciMarkus Armbruster2022-12-141-4/+2
* target/riscv: debug: Add initial support of type 6 triggerFrank Chang2022-09-271-4/+170
* target/riscv: debug: Check VU/VS modes for type 2 triggerFrank Chang2022-09-271-0/+10
* target/riscv: debug: Create common trigger actions functionFrank Chang2022-09-271-2/+57
* target/riscv: debug: Introduce tinfo CSRFrank Chang2022-09-271-3/+7
* target/riscv: debug: Restrict the range of tselect value can be writtenFrank Chang2022-09-271-6/+3
* target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRsFrank Chang2022-09-271-65/+38
* target/riscv: debug: Introduce build_tdata1() to build tdata1 register contentFrank Chang2022-09-271-5/+10
* target/riscv: debug: Determine the trigger type from tdata1.typeFrank Chang2022-09-271-55/+133
* target/riscv/debug.c: keep experimental rv128 support workingFrédéric Pétrot2022-06-101-0/+2
* target/riscv: csr: Hook debug CSR read/writeBin Meng2022-04-221-0/+27
* target/riscv: debug: Implement debug related TCGCPUOpsBin Meng2022-04-221-0/+75
* target/riscv: Add initial support for the Sdtrig extensionBin Meng2022-04-221-0/+339