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* [INTERP] Yet another opcode name comment fixptitSeb2025-04-241-1/+1
* [SIGNAL] Better signal logging when trace enabled (#2572)Yang Liu2025-04-241-2/+11
* [RV64_DYNAREC] Fixed x87 cache swapping (#2571)Yang Liu2025-04-242-9/+11
* [ARM64_DYNAREC] Small optim on (V)PACKUSDW opcodesptitSeb2025-04-242-14/+4
* [LA64_DYNAREC] Add/Opt more mmx/sse ops (#2565)phorcys2025-04-242-46/+180
* [INTERP] Cosmetic change to 0F 1C..1E opcodesptitSeb2025-04-241-3/+3
* [INTERP] Added nan handling on AVX.F3.0F 59 opcodeptitSeb2025-04-241-0/+2
* [ARM64_DYNAREC] Simplified code for MOVS[H/L]DUP opcodesptitSeb2025-04-242-19/+3
* [INTERP] Fixed another opcode name commentptitSeb2025-04-241-1/+1
* [LA64_DYNAREC] Add POPCNT/TZCNT/LZCNT ops. (#2566)phorcys2025-04-245-8/+170
* [ARM64_DYNAREC] Small iùprovments to some (V)MOVQ opcodesptitSeb2025-04-244-11/+12
* [INTERP] Fixed a commentptitSeb2025-04-241-1/+1
* [ARM64_DYNAREC] Small change and optims to various (V)MOVNT* opcodesptitSeb2025-04-244-33/+24
* [INTERP] Small change to various (V)MOVNT* opcodes, forbidding reg -> reg formptitSeb2025-04-246-56/+74
* [DYNAREC] Added ranged Dynablock dump (#2570)Yang Liu2025-04-2423-114/+116
* [ARM64_DYNAREC] Minor optim to MOVNTDQA (#2568)Yang Liu2025-04-241-3/+10
* Added some missing newlines (#2567)Yang Liu2025-04-241-2/+2
* [ARM64_DYNAREC] Small fixes and improvments to (V)MOVMSKP[S/D] opcodesptitSeb2025-04-234-15/+12
* [ARM64_DYNAREC] Few fixes and small cosmetic changes to some partial (V)MOV o...ptitSeb2025-04-238-58/+36
* [INTERP] Fex fixes and small cosmetic changes to some partial (V)MOV opcodesptitSeb2025-04-235-47/+80
* [ARM64_DYNAREC] Made REP MOVSB optimisation flaglessptitSeb2025-04-231-4/+4
* [ARM64_DYNAREC] Optimized REP STOSBptitSeb2025-04-232-2/+36
* [PERFMAP] Added x86 address of code when function name cannot be found, inste...ptitSeb2025-04-231-1/+4
* [ARM64_DYNAREC] Various improvment to various SSE/AVX 128bits/256bits mov op...ptitSeb2025-04-238-89/+144
* [INTERP] RaZ upper 128bits on vmov* Ex, Gx if Ex is a registry (unused?)ptitSeb2025-04-232-0/+6
* [RBTREE] Fixed an edge case (#2562)rajdakin2025-04-221-1/+3
* [DYNAREC] Added a x87pc test and some cosmetic changes too (#2561)Yang Liu2025-04-2216-158/+83
* [LA64_DYNAREC] Add SSSE3's mmx ops. (#2559)phorcys2025-04-221-0/+162
* [ARM64_DYNAREC] Improved (V)[MIN/MAX][S/P][S/D] opcodesptitSeb2025-04-224-34/+10
* [INTERP] Improved (V)[MIN/MAX][S/P][S/D] opcodesptitSeb2025-04-228-34/+25
* [RBTREE] Cache boundary nodes and remove `add_range()` (#2557)Chi-Kuan Chiu2025-04-221-31/+54
* [RV64_DYNAREC] Better handling of x87double=2 (#2560)Yang Liu2025-04-2210-1/+47
* [ARM64_DYNAREC] Small improvements to (V)MASKMOVDQU opcodeptitSeb2025-04-212-6/+4
* [ARM64_DYNAREC] Better handling of x87double=2ptitSeb2025-04-2110-0/+53
* [ARM64_DYNAREC] Fixed potential issue with (V)LDDQU opcodeptitSeb2025-04-212-3/+3
* [DYNAREC] More handling of low precision x87 flag change (#2556)Yang Liu2025-04-214-2/+8
* [INTERP] More fixes to INSERTQ/EXTRQ opcodesptitSeb2025-04-212-13/+17
* [RV64_DYNAREC][TRACE][COSIM] Improve x87 fiability in dynarec trace and cosim...Yang Liu2025-04-211-1/+1
* [ARM64_DYNAREC] Add/Improved (V)H[ADD/SUB]P[S/D] opcodesptitSeb2025-04-216-23/+53
* [ENV][COSIM] Enable x87double only if it's off (#2554)Yang Liu2025-04-211-1/+2
* [ARM64_DYNAREC] Small change to 66 0F 3A 17 opcodeptitSeb2025-04-211-2/+2
* [INTERP] Fixed EXTRQ opcodeptitSeb2025-04-211-3/+3
* [ARM64_DYNAREC] Minor cosmetic changesptitSeb2025-04-212-2/+2
* [INTERP] Better NAN handling for (V)DIV[P/S][S/D] opcodesptitSeb2025-04-213-0/+5
* [INTERP] VDPPD has no 256bits versionptitSeb2025-04-211-12/+2
* [RV64_DYNAREC] Added X87DOUBLE=2 support (#2553)Yang Liu2025-04-2122-24/+88
* [ARM64_DYNAREC] Another potential fix for X87DOUBLE=2ptitSeb2025-04-211-1/+1
* [ARM64_DYNAREC] Fixed some potential issues with BOX64_DYNAREC_DOUBLE=2ptitSeb2025-04-213-4/+1
* [TRACE] Fixed an issue with a trace on dynablock exiting executionptitSeb2025-04-211-1/+1
* [TRACE] Better trace, using maplile name if available, and better write on a ...ptitSeb2025-04-202-2/+5