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* hw/arm: Remove sl_bootparam_write() and 'hw/arm/sharpsl.h' headerPhilippe Mathieu-Daudé2025-10-071-17/+0
* hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5Frederic Konrad2025-10-071-0/+4
* hw/arm/xlnx-zynqmp: move GIC_NUM_SPI_INTR define in headerClément Chigot2025-10-071-0/+1
* hw/arm/xlnx-versal: add versal2 SoCLuc Michel2025-10-071-1/+16
* hw/misc/xlnx-versal-crl: add the versal2 versionLuc Michel2025-10-072-0/+330
* hw/arm/xlnx-versal: tidy upLuc Michel2025-10-071-204/+0
* hw/arm/xlnx-versal: use hw/arm/bsa.h for timer IRQ indicesLuc Michel2025-10-071-6/+0
* hw/misc/xlnx-versal-crl: refactor device reset logicLuc Michel2025-10-071-4/+4
* hw/misc/xlnx-versal-crl: split into base/concrete classesLuc Michel2025-10-071-2/+29
* hw/arm/xlnx-versal: add the versal_get_num_cpu accessorLuc Michel2025-10-071-0/+1
* hw/arm/xlnx-versal: ddr: refactor creationLuc Michel2025-10-071-5/+2
* hw/arm/xlnx-versal: ocm: refactor creationLuc Michel2025-10-071-4/+0
* hw/arm/xlnx-versal: rpu: refactor creationLuc Michel2025-10-071-11/+0
* hw/arm/xlnx-versal: add support for multiple GICsLuc Michel2025-10-071-0/+1
* hw/intc/arm_gicv3: Introduce a 'first-cpu-index' propertyFrancisco Iglesias2025-10-071-0/+1
* hw/arm/xlnx-versal: refactor CPU cluster creationLuc Michel2025-10-071-10/+2
* hw/arm/xlnx-versal-virt: virtio: refactor creationLuc Michel2025-10-071-0/+3
* hw/arm/xlnx-versal: crl: refactor creationLuc Michel2025-10-071-3/+0
* hw/arm/xlnx-versal: cfu: refactor creationLuc Michel2025-10-071-14/+0
* hw/arm/xlnx-versal: rtc: refactor creationLuc Michel2025-10-071-2/+0
* hw/arm/xlnx-versal: trng: refactor creationLuc Michel2025-10-071-2/+0
* hw/arm/xlnx-versal: bbram: refactor creationLuc Michel2025-10-071-2/+1
* hw/arm/xlnx-versal: PMC IOU SCLR: refactor creationLuc Michel2025-10-071-5/+0
* hw/arm/xlnx-versal: ospi: refactor creationLuc Michel2025-10-071-10/+2
* hw/arm/xlnx-versal: efuse: refactor creationLuc Michel2025-10-071-4/+1
* hw/arm/xlnx-versal: usb: refactor creationLuc Michel2025-10-071-5/+0
* hw/arm/xlnx-versal: xram: refactor creationLuc Michel2025-10-071-6/+0
* hw/arm/xlnx-versal: adma: refactor creationLuc Michel2025-10-071-2/+0
* hw/arm/xlnx-versal: gem: refactor creationLuc Michel2025-10-071-3/+0
* hw/arm/xlnx-versal: sdhci: refactor creationLuc Michel2025-10-071-2/+3
* hw/arm/xlnx-versal: canfd: refactor creationLuc Michel2025-10-071-3/+4
* hw/arm/xlnx-versal: uart: refactor creationLuc Michel2025-10-071-2/+0
* hw/arm/xlnx-versal: prepare for FDT creationLuc Michel2025-10-071-0/+12
* hw/arm/xlnx-versal: split the xlnx-versal typeLuc Michel2025-10-072-1/+26
* Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ...Richard Henderson2025-10-0628-41/+403
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| * virtio: improve virtqueue mapping error messagesAlessandro Ratti2025-10-051-0/+1
| * intel-iommu: Move dma_translation to x86-iommuJoao Martins2025-10-051-0/+1
| * virtio: unify virtio_notify_irqfd() and virtio_notify()Stefan Hajnoczi2025-10-051-1/+0
| * x86: ich9: fix default value of 'No Reboot' bit in GCSIgor Mammedov2025-10-051-1/+1
| * intel_iommu: Add PRI operations supportCLEMENT MATHIEU--DRIF2025-10-051-0/+1
| * pcie: Add a way to get the outstanding page request allocation (pri) from the...CLEMENT MATHIEU--DRIF2025-10-051-0/+1
| * hw/virtio: rename vhost-user-device and make user creatableAlex Bennée2025-10-051-1/+1
| * pcie_sriov: Fix broken MMIO accesses from SR-IOV VFsDamien Bergamini2025-10-051-4/+0
| * hw/smbios: allow clearing the VM bit in SMBIOS table 0Daniil Tatianin2025-10-051-1/+1
| * qapi/acpi-hest: add an interface to do generic CPER error injectionMauro Carvalho Chehab2025-10-052-0/+2
| * arm/virt: Wire up a GED error device for ACPI / GHESMauro Carvalho Chehab2025-10-051-0/+1
| * acpi/generic_event_device: add an APEI error deviceMauro Carvalho Chehab2025-10-043-0/+4
| * acpi/ghes: add a notifier to notify when error data is readyMauro Carvalho Chehab2025-10-041-0/+3
| * acpi/ghes: don't hard-code the number of sources for HEST tableMauro Carvalho Chehab2025-10-041-5/+12
| * acpi/ghes: Use HEST table offsets when preparing GHES recordsMauro Carvalho Chehab2025-10-041-1/+1