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* target/arm: Add isar feature test for FEAT_RME_GPC2Richard Henderson2025-10-071-0/+5
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250926001134.295547-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Implement ID_AA64PFR2_EL1Peter Maydell2025-09-261-0/+5
| | | | | | | | | | | | | | | | | | Currently we define the ID_AA64PFR2_EL1 encoding as reserved (with the required RAZ behaviour for unassigned system registers in the ID register encoding space). Newer architecture versions start to define fields in this ID register, so define the appropriate constants and implement it as an ID register backed by a field in cpu->isar. Since none of our CPUs set that isar field to non-zero, there is no behavioural change here (other than the name exposed to the user via the gdbstub), but this paves the way for implementing the new features that use fields in this register. The fields here are the ones documented in rev L.b of the Arm ARM. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* target/arm: Move ID register field defs to cpu-features.hPeter Maydell2025-09-261-0/+410
| | | | | | | | | | | | | | | | Currently we define constants for the ID register fields in cpu.h. This means they're defined for a lot more code in QEMU than actually needs them. Move them to cpu-features.h, which is where we define the feature functions that test fields in these registers. There's only one place where we need to use some of these macro definitions that we weren't already including cpu-features.h: linux-user/arm/target_proc.h. Otherwise this patch is a pure movement of code from one file to the other. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* target/arm: Implement FEAT_ATS1ARichard Henderson2025-09-161-0/+5
| | | | | | | | | Implement FEAT_ATS1A and enable for -cpu max. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250830054128.448363-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Implement FEAT_LSE128Richard Henderson2025-08-301-0/+5
| | | | | | | | | This feature contains the LDCLRP, LDSETP, and SWPP instructions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250815122653.701782-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Rename isar_feature_aa64_atomicsRichard Henderson2025-08-301-1/+1
| | | | | | | | | | | This is FEAT_LSE -- rename the predicate to match. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250830045006.380393-1-richard.henderson@linaro.org Message-id: 20250815122653.701782-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Correct condition of aa64_atomics feature functionPeter Maydell2025-08-301-1/+1
| | | | | | | | | | | | | | | The ARMv8.1-Atomics feature (renamed FEAT_LSE in more modern versions of the Arm ARM) has always ben indicated by ID_AA64ISAR0.ATOMIC being 0b0010 or greater; 0b0001 is a reserved unused value. We were incorrectly checking for != 0; this had no harmful effects because all the CPUs set their value for this field to either 0 (for not having the feature) or 2 (if they do have it), but it's better to match what the architecture specifies here. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250819145659.2165160-1-peter.maydell@linaro.org
* target/arm: Add feature predicate for FEAT_CSSCRichard Henderson2025-08-301-0/+5
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250803014019.416797-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Implement FEAT_TCR2 and enable with -cpu maxGustavo Romero2025-08-301-0/+5
| | | | | | | | | | | | | | | | Add FEAT_TCR2, which introduces the TCR2_EL1 and TCR2_EL2 registers. These registers are extensions of the TCR_ELx registers and provide top-level control of the EL10 and EL20 translation regimes. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250727074202.83141-5-richard.henderson@linaro.org Message-ID: <20250711140828.1714666-5-gustavo.romero@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [rth: Remove FEAT_MEC code; handle SCR and HCRX enable bits.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Implement FEAT_SCTLR2 and enable with -cpu maxGustavo Romero2025-08-301-0/+5
| | | | | | | | | | | | | | | Add FEAT_SCTLR2, which introduces the SCTLR2_EL1, SCTLR2_EL2, and SCTLR2_EL3 registers. These registers are extensions of the SCTLR_ELx ones. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250727074202.83141-4-richard.henderson@linaro.org Message-ID: <20250711140828.1714666-4-gustavo.romero@linaro.org> [rth: Remove FEAT_MEC code; handle SCR and HCRX enable bits.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Add isar feature tests for SME2p1, SVE2p1Richard Henderson2025-07-041-0/+63
| | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm/cpu: Store id_mmfr0-5 into the idregs arrayEric Auger2025-07-011-9/+9
| | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-12-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm/cpu: Store id_dfr0/1 into the idregs arrayEric Auger2025-07-011-8/+8
| | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-11-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm/cpu: Store id_pfr0/1/2 into the idregs arrayEric Auger2025-07-011-5/+5
| | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-10-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm/cpu: Store id_isar0-7 into the idregs arrayEric Auger2025-07-011-18/+18
| | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-9-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm/cpu: Store aa64smfr0 into the idregs arrayEric Auger2025-07-011-3/+3
| | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-8-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm/cpu: Store aa64dfr0/1 into the idregs arrayEric Auger2025-07-011-8/+8
| | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-7-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm/cpu: Store aa64mmfr0-3 into the idregs arrayEric Auger2025-07-011-37/+37
| | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-6-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm/cpu: Store aa64pfr0/1 into the idregs arrayEric Auger2025-07-011-20/+20
| | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-5-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm/cpu: Store aa64isar1/2 into the idregs arrayEric Auger2025-07-011-22/+22
| | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-4-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm/cpu: Store aa64isar0/aa64zfr0 into the idregs arraysEric Auger2025-07-011-28/+29
| | | | | | | | | | | Also add kvm accessors for storing host features into idregs. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-3-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm/cpu-features: Include missing 'cpu.h' headerPhilippe Mathieu-Daudé2025-05-291-0/+1
| | | | | | | | | | | | | | | | | | | "target/arm/cpu-features.h" dereferences the ARMISARegisters structure, which is defined in "cpu.h". Include the latter to avoid when refactoring unrelated headers: In file included from target/arm/internals.h:33: target/arm/cpu-features.h:45:54: error: unknown type name 'ARMISARegisters' 45 | static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) | ^ target/arm/cpu-features.h:47:12: error: use of undeclared identifier 'R_ID_ISAR0_DIVIDE_SHIFT' 47 | return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; | ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250513173928.77376-7-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Plumb FEAT_RPRES frecpe and frsqrte through to new helperPeter Maydell2025-02-111-0/+5
| | | | | | | | | | | | | | | | FEAT_RPRES implements an "increased precision" variant of the single precision FRECPE and FRSQRTE instructions from an 8 bit to a 12 bit mantissa. This applies only when FPCR.AH == 1. Note that the halfprec and double versions of these insns retain the 8 bit precision regardless. In this commit we add all the plumbing to make these instructions call a new helper function when the increased-precision is in effect. In the following commit we will provide the actual change in behaviour in the helpers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* target/arm: Define FPCR AH, FIZ, NEP bitsPeter Maydell2025-02-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Armv8.7 FEAT_AFP feature defines three new control bits in the FPCR: * FPCR.AH: "alternate floating point mode"; this changes floating point behaviour in a variety of ways, including: - the sign of a default NaN is 1, not 0 - if FPCR.FZ is also 1, denormals detected after rounding with an unbounded exponent has been applied are flushed to zero - FPCR.FZ does not cause denormalized inputs to be flushed to zero - miscellaneous other corner-case behaviour changes * FPCR.FIZ: flush denormalized numbers to zero on input for most instructions * FPCR.NEP: makes scalar SIMD operations merge the result with higher vector elements in one of the source registers, instead of zeroing the higher elements of the destination This commit defines the new bits in the FPCR, and allows them to be read or written when FEAT_AFP is implemented. Actual behaviour changes will be implemented in subsequent commits. Note that these are the first FPCR bits which don't appear in the AArch32 FPSCR view of the register, and which share bit positions with FPSR bits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* target/arm: Implement fine-grained-trap handling for FEAT_XSPeter Maydell2024-12-171-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | FEAT_XS introduces a set of new TLBI maintenance instructions with an "nXS" qualifier. These behave like the stardard ones except that they do not wait for memory accesses with the XS attribute to complete. They have an interaction with the fine-grained-trap handling: the FGT bits that a hypervisor can use to trap TLBI maintenance instructions normally trap also the nXS variants, but the hypervisor can elect to not trap the nXS variants by setting HCRX_EL2.FGTnXS to 1. Add support to our FGT mechanism for these TLBI bits. For each TLBI-trapping FGT bit we define, for example: * FGT_TLBIVAE1 -- the same value we do at present for the normal variant of the insn * FGT_TLBIVAE1NXS -- for the nXS qualified insn; the value of this enum has an NXS bit ORed into it In access_check_cp_reg() we can then ignore the trap bit for an access where ri->fgt has the NXS bit set and HCRX_EL2.FGTnXS is 1. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211144440.2700268-2-peter.maydell@linaro.org
* target/arm: Enable FEAT_CMOW for -cpu maxGustavo Romero2024-11-051-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FEAT_CMOW introduces support for controlling cache maintenance instructions executed in EL0/1 and is mandatory from Armv8.8. On real hardware, the main use for this feature is to prevent processes from invalidating or flushing cache lines for addresses they only have read permission, which can impact the performance of other processes. QEMU implements all cache instructions as NOPs, and, according to rule [1], which states that generating any Permission fault when a cache instruction is implemented as a NOP is implementation-defined, no Permission fault is generated for any cache instruction when it lacks read and write permissions. QEMU does not model any cache topology, so the PoU and PoC are before any cache, and rules [2] apply. These rules state that generating any MMU fault for cache instructions in this topology is also implementation-defined. Therefore, for FEAT_CMOW, we do not generate any MMU faults either, instead, we only advertise it in the feature register. [1] Rule R_HGLYG of section D8.14.3, Arm ARM K.a. [2] Rules R_MZTNR and R_DNZYL of section D8.14.3, Arm ARM K.a. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241104142606.941638-1-gustavo.romero@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm/tcg: refine cache descriptions with a wrapperAlireza Sanaee2024-09-131-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | This patch allows for easier manipulation of the cache description register, CCSIDR. Which is helpful for testing as well. Currently, numbers get hard-coded and might be prone to errors. Therefore, this patch adds a wrapper for different types of CPUs available in tcg to decribe caches. One function `make_ccsidr` supports two cases by carrying a parameter as FORMAT that can be LEGACY and CCIDX which determines the specification of the register. For CCSIDR register, 32 bit version follows specification [1]. Conversely, 64 bit version follows specification [2]. [1] B4.1.19, ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition, https://developer.arm.com/documentation/ddi0406 [2] D23.2.29, ARM Architecture Reference Manual for A-profile Architecture, https://developer.arm.com/documentation/ddi0487/latest/ Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240903144550.280-1-alireza.sanaee@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Allow setting the FPCR.EBF bit for FEAT_EBF16Peter Maydell2024-09-051-0/+5
| | | | | | | | | | | | FEAT_EBF16 adds one new bit to the FPCR floating point control register. Allow this bit to be read and written when the ID registers indicate the presence of the feature. Note that because this new bit is not in FPSCR_FPCR_MASK the bit is not visible in the AArch32 FPSCR, and FPSCR writes do not affect it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* target/arm: Implement FEAT WFxT and enable for '-cpu max'Peter Maydell2024-05-301-0/+5
| | | | | | | | | | | | | | | | | | | | FEAT_WFxT introduces new instructions WFIT and WFET, which are like the existing WFI and WFE but allow the guest to pass a timeout value in a register. The instructions will wait for an interrupt/event as usual, but will also stop waiting when the value of CNTVCT_EL0 is greater than or equal to the specified timeout value. We implement WFIT by setting up a timer to expire at the right point; when the timer expires it sets the EXITTB interrupt, which will cause the CPU to leave the halted state. If we come out of halt for some other reason, we unset the pending timer. We implement WFET as a nop, which is architecturally permitted and matches the way we currently make WFE a nop. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240430140035.3889879-3-peter.maydell@linaro.org
* target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMIJinjie Ruan2024-04-251-0/+5
| | | | | | | | | | | | FEAT_NMI defines another three new bits in HCRX_EL2: TALLINT, HCRX_VINMI and HCRX_VFNMI. When the feature is enabled, allow these bits to be written in HCRX_EL2. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-2-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Implement FEAT_ECV CNTPOFF_EL2 handlingPeter Maydell2024-03-071-0/+5
| | | | | | | | | | | | | | When ID_AA64MMFR0_EL1.ECV is 0b0010, a new register CNTPOFF_EL2 is implemented. This is similar to the existing CNTVOFF_EL2, except that it controls a hypervisor-adjustable offset made to the physical counter and timer. Implement the handling for this register, which includes control/trap bits in SCR_EL3 and CNTHCTL_EL2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240301183219.2424889-8-peter.maydell@linaro.org
* target/arm: Implement new FEAT_ECV trap bitsPeter Maydell2024-03-071-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | The functionality defined by ID_AA64MMFR0_EL1.ECV == 1 is: * four new trap bits for various counter and timer registers * the CNTHCTL_EL2.EVNTIS and CNTKCTL_EL1.EVNTIS bits which control scaling of the event stream. This is a no-op for us, because we don't implement the event stream (our WFE is a NOP): all we need to do is allow CNTHCTL_EL2.ENVTIS to be read and written. * extensions to PMSCR_EL1.PCT, PMSCR_EL2.PCT, TRFCR_EL1.TS and TRFCR_EL2.TS: these are all no-ops for us, because we don't implement FEAT_SPE or FEAT_TRF. * new registers CNTPCTSS_EL0 and NCTVCTSS_EL0 which are "self-sychronizing" views of the CNTPCT_EL0 and CNTVCT_EL0, meaning that no barriers are needed around their accesses. For us these are just the same as the normal views, because all our sysregs are inherently self-sychronizing. In this commit we implement the trap handling and permit the new CNTHCTL_EL2 bits to be written. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240301183219.2424889-6-peter.maydell@linaro.org
* target/arm: Fix incorrect aa64_tidcp1 feature checkPeter Maydell2024-01-261-1/+1
| | | | | | | | | | | | | | A typo in the implementation of isar_feature_aa64_tidcp1() means we were checking the field in the wrong ID register, so we might have provided the feature on CPUs that don't have it and not provided it on CPUs that should have it. Correct this bug. Cc: qemu-stable@nongnu.org Fixes: 9cd0c0dec97be9 "target/arm: Implement FEAT_TIDCP1" Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2120 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240123160333.958841-1-peter.maydell@linaro.org
* target/arm/cpu-features: Include missing 'hw/registerfields.h' headerPhilippe Mathieu-Daudé2024-01-261-0/+2
| | | | | | | | | | | | | | | | target/arm/cpu-features.h uses the FIELD_EX32() macro defined in "hw/registerfields.h". Include it in order to avoid when refactoring unrelated headers: target/arm/cpu-features.h:44:12: error: call to undeclared function 'FIELD_EX32'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-6-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Handle HCR_EL2 accesses for FEAT_NV2 bitsPeter Maydell2024-01-091-0/+5
| | | | | | | | | FEAT_NV2 defines another new bit in HCR_EL2: NV2. When the feature is enabled, allow this bit to be written in HCR_EL2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Miguel Luis <miguel.luis@oracle.com>
* target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NVPeter Maydell2024-01-091-0/+5
| | | | | | | | | | FEAT_NV defines three new bits in HCR_EL2: NV, NV1 and AT. When the feature is enabled, allow these bits to be written, and flush the TLBs for the bits which affect page table interpretation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Miguel Luis <miguel.luis@oracle.com>
* linux-user/elfload: Add missing arm64 hwcap valuesMarielle Novastrider2023-11-021-0/+5
| | | | | | | | | | | | | | Specifically DIT, LSE2, and MTE3. We already expose detection of these via the CPUID interface, but missed these from ELF hwcaps. Signed-off-by: Marielle Novastrider <marielle@novastrider.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20231029210058.38986-1-marielle@novastrider.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fixed conflict with feature tests moving to cpu-features.h] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Move ID_AA64DFR* feature tests togetherPeter Maydell2023-10-271-5/+5
| | | | | | | | | Move all the ID_AA64DFR* feature test functions together. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-7-peter.maydell@linaro.org
* target/arm: Move ID_AA64PFR* tests togetherPeter Maydell2023-10-271-43/+43
| | | | | | | | | Move all the ID_AA64PFR* feature test functions together. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-6-peter.maydell@linaro.org
* target/arm: Move ID_AA64ISAR* test functions togetherPeter Maydell2023-10-271-35/+35
| | | | | | | | | | Move the feature test functions that test ID_AA64ISAR* fields together. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-5-peter.maydell@linaro.org
* target/arm: Move ID_AA64MMFR0 tests up to before MMFR1 and MMFR2Peter Maydell2023-10-271-60/+60
| | | | | | | | | | Move the ID_AA64MMFR0 feature test functions up so they are before the ones for ID_AA64MMFR1 and ID_AA64MMFR2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-4-peter.maydell@linaro.org
* target/arm: Move ID_AA64MMFR1 and ID_AA64MMFR2 tests togetherPeter Maydell2023-10-271-30/+30
| | | | | | | | | | | | | Our list of isar_feature functions is not in any particular order, but tests on fields of the same ID register tend to be grouped together. A few functions that are tests of fields in ID_AA64MMFR1 and ID_AA64MMFR2 are not in the same place as the rest; move them into their groups. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-3-peter.maydell@linaro.org
* target/arm: Move feature test functions to their own headerPeter Maydell2023-10-271-0/+994
The feature test functions isar_feature_*() now take up nearly a thousand lines in target/arm/cpu.h. This header file is included by a lot of source files, most of which don't need these functions. Move the feature test functions to their own header file. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-2-peter.maydell@linaro.org