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path: root/target/mips/cpu.h (follow)
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* target: Define TCG_GUEST_DEFAULT_MO in 'cpu-param.h'Philippe Mathieu-Daudé2024-04-261-2/+0
* target/mips: Remove CPUMIPSState::CP0_SAARI fieldPhilippe Mathieu-Daudé2024-02-151-1/+0
* target/mips: Remove CPUMIPSState::CP0_SAAR[2] fieldPhilippe Mathieu-Daudé2024-02-151-1/+0
* target/mips: Remove CPUMIPSState::saarp fieldPhilippe Mathieu-Daudé2024-02-151-1/+0
* target/mips: Remove MIPSITUState::itu fieldPhilippe Mathieu-Daudé2024-02-151-1/+0
* target/mips: Use qemu_irq typedef for CPUMIPSState::irq memberPhilippe Mathieu-Daudé2024-02-151-1/+1
* include/exec: Implement cpu_mmu_index genericallyRichard Henderson2024-02-031-5/+0
* target/mips: Split out mips_env_mmu_indexRichard Henderson2024-02-031-1/+6
* target/mips: Pass ptw_mmu_idx down from mips_cpu_tlb_fillRichard Henderson2024-02-031-1/+3
* target/mips: Use generic cpu_list()Gavin Shan2024-01-051-4/+0
* target: Move ArchCPUClass definition to 'cpu.h'Philippe Mathieu-Daudé2023-11-071-0/+17
* target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'Philippe Mathieu-Daudé2023-11-071-2/+0
* target: Unify QOM stylePhilippe Mathieu-Daudé2023-11-071-2/+0
* hw/misc/mips_itu: Declare itc_reconfigure() in 'hw/misc/mips_itu.h'Philippe Mathieu-Daudé2023-10-191-3/+0
* hw/mips: Merge 'hw/mips/cpudevs.h' with 'target/mips/cpu.h'Philippe Mathieu-Daudé2023-10-191-1/+3
* accel/tcg: Move CPUNegativeOffsetState into CPUStateRichard Henderson2023-10-031-2/+2
* bulk: Do not declare function prototypes using 'extern' keywordPhilippe Mathieu-Daudé2023-08-311-2/+2
* target/mips: Implement Loongson CSR instructionsJiaxun Yang2023-07-101-0/+42
* target/mips: Rework cp0_timer with clock APIJiaxun Yang2023-07-101-1/+2
* target: Widen pc/cs_base in cpu_get_tb_cpu_stateAnton Johansson2023-06-261-2/+2
* target/mips: Implement CP0.Config7.WII bit supportMarcin Nowakowski2023-03-081-0/+1
* mips: Remove support for trap and emulate KVMPaolo Bonzini2023-01-131-3/+0
* target/mips: Use an exception for semihostingRichard Henderson2022-06-281-1/+2
* target/mips: Fix emulation of nanoMIPS BPOSGE32C instructionDragan Mladjenovic2022-06-111-1/+1
* target/mips: Fix WatchHi.M handlingMarcin Nowakowski2022-06-111-0/+1
* Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau2022-04-061-1/+1
* Merge remote-tracking branch 'remotes/philmd/tags/mips-20220308' into stagingPeter Maydell2022-03-091-9/+0
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| * target/mips: Remove duplicated MIPSCPU::cp0_count_ratePhilippe Mathieu-Daudé2022-03-071-9/+0
* | target: Use ArchCPU as interface to target CPUPhilippe Mathieu-Daudé2022-03-061-1/+1
* | target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macroPhilippe Mathieu-Daudé2022-03-061-2/+0
* | target: Use CPUArchState as interface to target-specific CPU statePhilippe Mathieu-Daudé2022-03-061-4/+2
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* include/exec: Move cpu_signal_handler declarationRichard Henderson2021-09-211-3/+0
* target/mips: Restrict some system specific declarations to sysemuPhilippe Mathieu-Daudé2021-06-241-3/+7
* target/mips: Promote 128-bit multimedia registers as global onesPhilippe Mathieu-Daudé2021-02-211-3/+7
* target/mips: Remove unused MMU definitionsPhilippe Mathieu-Daudé2021-02-211-16/+0
* target/mips: Introduce ase_msa_available() helperPhilippe Mathieu-Daudé2021-01-141-0/+6
* target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()Philippe Mathieu-Daudé2021-01-141-0/+5
* target/mips/addr: Add translation helpers for KSEG1Jiaxun Yang2021-01-141-0/+2
* target/mips: Add CP0 Config0 register definitions for MIPS3 ISAPhilippe Mathieu-Daudé2021-01-141-1/+9
* linux-user/elfload: Introduce MIPS GET_FEATURE_REG_EQU() macroPhilippe Mathieu-Daudé2020-12-171-0/+1
* target/mips: Introduce ase_mt_available() helperPhilippe Mathieu-Daudé2020-12-131-0/+7
* hw/mips: Move address translation helpers to target/mips/Philippe Mathieu-Daudé2020-12-131-0/+8
* target/mips: Introduce cpu_supports_isa() taking CPUMIPSState argumentPhilippe Mathieu-Daudé2020-12-131-0/+1
* target/mips: Rename cpu_supports_FEAT() as cpu_type_supports_FEAT()Philippe Mathieu-Daudé2020-12-131-2/+2
* target/mips: Fix PageMask with variable page sizeJiaxun Yang2020-11-091-0/+1
* target/mips/cpu: Introduce mips_cpu_create_with_clock() helperPhilippe Mathieu-Daudé2020-10-171-0/+12
* target/mips/cpu: Allow the CPU to use dynamic frequenciesPhilippe Mathieu-Daudé2020-10-171-0/+4
* target/mips/cpu: Make cp0_count_rate a propertyPhilippe Mathieu-Daudé2020-10-171-0/+9
* target/mips: Move cp0_count_ns to CPUMIPSStatePhilippe Mathieu-Daudé2020-10-171-0/+1
* target/mips: Add Loongson-3 CPU definitionHuacai Chen2020-06-091-2/+30