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path: root/target/riscv/debug.h (follow)
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* exec: Declare CPUBreakpoint/CPUWatchpoint type in 'breakpoint.h' headerPhilippe Mathieu-Daudé2024-04-261-0/+2
* target/riscv: Allocate itrigger timers only onceAkihiko Odaki2023-09-111-1/+2
* target/riscv: Add itrigger support when icount is enabledLIU Zhiwei2023-01-061-0/+1
* target/riscv: Add itrigger support when icount is not enabledLIU Zhiwei2023-01-061-0/+12
* target/riscv: debug: Add initial support of type 6 triggerFrank Chang2022-09-271-0/+18
* target/riscv: debug: Create common trigger actions functionFrank Chang2022-09-271-0/+13
* target/riscv: debug: Introduce tinfo CSRFrank Chang2022-09-271-0/+2
* target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRsFrank Chang2022-09-271-7/+0
* target/riscv: debug: Introduce build_tdata1() to build tdata1 register contentFrank Chang2022-09-271-0/+2
* target/riscv: debug: Determine the trigger type from tdata1.typeFrank Chang2022-09-271-9/+4
* target/riscv: csr: Hook debug CSR read/writeBin Meng2022-04-221-0/+2
* target/riscv: debug: Implement debug related TCGCPUOpsBin Meng2022-04-221-0/+4
* target/riscv: Add initial support for the Sdtrig extensionBin Meng2022-04-221-0/+108