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path: root/target/arm/cpu.h (follow)
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| * target/arm: Add TBFLAG_M32.SECURERichard Henderson2022-10-101-0/+2
| * target/arm: allow setting SCR_EL3.EnTP2 when FEAT_SME is implementedJerome Forissier2022-10-101-27/+27
* | dump: Replace opaque DumpState pointer with a typed oneJanosch Frank2022-10-061-2/+2
|/
* target/arm: Update SDCR_VALID_MASK to include SCCDPeter Maydell2022-09-291-1/+7
* target/arm: Support 64-bit event counters for FEAT_PMUv3p5Peter Maydell2022-09-141-0/+1
* target/arm: Implement FEAT_PMUv3p5 cycle counter disable bitsPeter Maydell2022-09-141-0/+20
* target/arm: Rename pmu_8_n feature test functionsPeter Maydell2022-09-141-8/+8
* target/arm: Implement ID_DFR1Peter Maydell2022-09-141-0/+1
* target/arm: Implement ID_MMFR5Peter Maydell2022-09-141-0/+1
* target/arm: Add MO_128 entry to pred_esz_masks[]Peter Maydell2022-07-261-1/+1
* target/arm: Honour VTCR_EL2 bits in Secure EL2Peter Maydell2022-07-181-0/+19
* target/arm: Store TCR_EL* registers as uint64_tPeter Maydell2022-07-181-7/+1
* target/arm: Store VTCR_EL2, VSTCR_EL2 registers as uint64_tPeter Maydell2022-07-181-2/+2
* linux-user/aarch64: Do not clear PROT_MTE on mprotectRichard Henderson2022-07-181-2/+5
* target/arm: Trap non-streaming usage when Streaming SVE is activeRichard Henderson2022-07-111-0/+7
* target/arm: Correctly implement Feat_DoubleLockPeter Maydell2022-07-071-0/+20
* target/arm: Implement AArch32 DBGDEVID, DBGDEVID1, DBGDEVID2Peter Maydell2022-07-071-0/+7
* target/arm: Add SVL to TB flagsRichard Henderson2022-06-271-0/+12
* target/arm: Introduce sve_vqm1_for_el_smRichard Henderson2022-06-271-2/+7
* target/arm: Add cpu properties for SMERichard Henderson2022-06-271-0/+2
* target/arm: Unexport aarch64_add_*_propertiesRichard Henderson2022-06-271-3/+0
* target/arm: Move arm_cpu_*_finalize to internals.hRichard Henderson2022-06-271-6/+0
* target/arm: Create ARMVQMapRichard Henderson2022-06-271-15/+14
* target/arm: Implement SMSTART, SMSTOPRichard Henderson2022-06-271-0/+1
* target/arm: Add the SME ZA storage to CPUARMStateRichard Henderson2022-06-271-0/+22
* target/arm: Add PSTATE.{SM,ZA} to TB flagsRichard Henderson2022-06-271-0/+2
* target/arm: Add SMCR_ELxRichard Henderson2022-06-271-2/+6
* target/arm: Add SVCRRichard Henderson2022-06-271-0/+6
* target/arm: Add SMEEXC_EL to TB flagsRichard Henderson2022-06-271-0/+2
* target/arm: Implement TPIDR2_EL0Richard Henderson2022-06-271-0/+1
* target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12]Richard Henderson2022-06-101-0/+5
* target/arm: Move arm_debug_target_el to debug_helper.cRichard Henderson2022-06-101-21/+0
* target/arm: Remove TBFLAG_ANY.DEBUG_TARGET_ELRichard Henderson2022-06-101-4/+2
* target/arm: Move arm_generate_debug_exceptions out of lineRichard Henderson2022-06-101-91/+0
* target/arm: Move arm_singlestep_active out of lineRichard Henderson2022-06-101-10/+0
* target/arm: Add ID_AA64SMFR0_EL1Richard Henderson2022-06-081-0/+25
* target/arm: Add isar_feature_aa64_smeRichard Henderson2022-06-081-0/+5
* target/arm: Rename sve_zcr_len_for_el to sve_vqm1_for_elRichard Henderson2022-06-081-1/+10
* target/arm: Use uint32_t instead of bitmap for sve vq'sRichard Henderson2022-06-081-3/+3
* linux-user/aarch64: Introduce sve_vqRichard Henderson2022-06-081-0/+11
* target/arm: Rename TBFLAG_A64 ZCR_LEN to VLRichard Henderson2022-06-081-1/+2
* target/arm: Implement FEAT_DoubleFaultPeter Maydell2022-06-081-0/+5
* target/arm: Use FIELD definitions for CPACR, CPTR_ELxRichard Henderson2022-05-191-5/+39
* target/arm: Enable FEAT_HCX for -cpu maxRichard Henderson2022-05-191-0/+20
* target/arm: Make number of counters in PMCR follow the CPUPeter Maydell2022-05-191-0/+1
* hw/intc/arm_gicv3: Use correct number of priority bits for the CPUPeter Maydell2022-05-191-0/+1
* target/arm: Implement FEAT_IDSTPeter Maydell2022-05-191-0/+5
* target/arm: Implement FEAT_S2FWBPeter Maydell2022-05-191-0/+5
* target/arm: Enable FEAT_CSV2_2 for -cpu maxRichard Henderson2022-05-091-0/+16
* target/arm: Implement virtual SError exceptionsRichard Henderson2022-05-091-0/+2