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* target/mips: Add implementation of GINVT instructionYongbok Kim2020-01-291-1/+1
| | | | | | | | | | | | Implement emulation of GINVT instruction. As QEMU doesn't support caches and virtualization, this implementation covers only one instruction (GINVT - Global Invalidate TLB) among all TLB-related MIPS instructions. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1579883929-1517-5-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: Amend CP0 WatchHi register implementationYongbok Kim2020-01-291-1/+1
| | | | | | | | | | | WatchHi is extended by the field MemoryMapID with the GINVT instruction. The field is accessible by MTHC0/MFHC0 in 32-bit architectures and DMTC0/ DMFC0 in 64-bit architectures. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1579883929-1517-4-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIXRichard Henderson2020-01-151-4/+0
| | | | | | | | | | | | | | The separate suffixed functions were used to construct some do_##insn function switched on mmu_idx. The interface is exactly identical to the *_mmuidx_ra functions. Replace them directly and remove the constructions. Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/mips: Clean up handling of CP0 register 31Aleksandar Markovic2019-08-291-1/+1
| | | | | | | | Clean up handling of CP0 register 31. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-31-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: Clean up handling of CP0 register 29Aleksandar Markovic2019-08-291-8/+14
| | | | | | | | Clean up handling of CP0 register 29. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-29-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: Clean up handling of CP0 register 28Aleksandar Markovic2019-08-291-10/+14
| | | | | | | | Clean up handling of CP0 register 28. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-28-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: Clean up handling of CP0 register 26Aleksandar Markovic2019-08-291-1/+1
| | | | | | | | Clean up handling of CP0 register 26. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-26-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: Clean up handling of CP0 register 23Aleksandar Markovic2019-08-291-0/+6
| | | | | | | | Clean up handling of CP0 register 23. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-23-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: Clean up handling of CP0 register 19Aleksandar Markovic2019-08-291-0/+4
| | | | | | | | Clean up handling of CP0 register 19. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-21-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: Clean up handling of CP0 register 18Aleksandar Markovic2019-08-291-8/+12
| | | | | | | | Clean up handling of CP0 register 18. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-20-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: Clean up handling of CP0 register 16Aleksandar Markovic2019-08-291-1/+2
| | | | | | | | Clean up handling of CP0 register 16. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-18-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: Clean up handling of CP0 register 15Aleksandar Markovic2019-08-291-0/+1
| | | | | | | | Clean up handling of CP0 register 15. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-17-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: Clean up handling of CP0 register 14Aleksandar Markovic2019-08-291-0/+1
| | | | | | | | Clean up handling of CP0 register 14. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-16-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: Clean up handling of CP0 register 13Aleksandar Markovic2019-08-291-0/+2
| | | | | | | | Clean up handling of CP0 register 13. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-15-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: Clean up handling of CP0 register 12Aleksandar Markovic2019-08-291-0/+3
| | | | | | | | Clean up handling of CP0 register 12. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-14-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: Clean up handling of CP0 register 10Aleksandar Markovic2019-08-291-0/+1
| | | | | | | | Clean up handling of CP0 register 10. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-12-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: Clean up handling of CP0 register 8Aleksandar Markovic2019-08-291-0/+1
| | | | | | | | Clean up handling of CP0 register 8. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-10-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: Clean up handling of CP0 register 6Aleksandar Markovic2019-08-291-0/+6
| | | | | | | | Clean up handling of CP0 register 6. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-8-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: Clean up handling of CP0 register 5Aleksandar Markovic2019-08-291-0/+6
| | | | | | | | Clean up handling of CP0 register 5. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-7-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: Clean up handling of CP0 register 4Aleksandar Markovic2019-08-291-0/+2
| | | | | | | | Clean up handling of CP0 register 4. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-6-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: Clean up handling of CP0 register 3Aleksandar Markovic2019-08-291-0/+1
| | | | | | | | Clean up handling of CP0 register 3. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-5-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: Clean up handling of CP0 register 2Aleksandar Markovic2019-08-291-0/+7
| | | | | | | | Clean up handling of CP0 register 2. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-4-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: Clean up handling of CP0 register 1Aleksandar Markovic2019-08-291-0/+8
| | | | | | | | Clean up handling of CP0 register 1. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-3-git-send-email-aleksandar.markovic@rt-rk.com>
* target/mips: Clean up handling of CP0 register 0Aleksandar Markovic2019-08-291-0/+3
| | | | | | | | Clean up handling of CP0 register 0. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-2-git-send-email-aleksandar.markovic@rt-rk.com>
* configure: Define target access alignment in configuretony.nguyen@bt.com2019-08-201-2/+0
| | | | | | | | | | | | | This patch moves the define of target access alignment earlier from target/foo/cpu.h to configure. Suggested in Richard Henderson's reply to "[PATCH 1/4] tcg: TCGMemOp is now accelerator independent MemOp" Signed-off-by: Tony Nguyen <tony.nguyen@bt.com> Message-Id: <11e818d38ebc40e986cfa62dd7d0afdc@tpw09926dag18e.domain1.systemhost.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: tony.nguyen@bt.com <tony.nguyen@bt.com>
* target/mips: rationalise softfloat includesAlex Bennée2019-08-191-7/+1
| | | | | | | | | | | | We should avoid including the whole of softfloat headers in cpu.h and explicitly include it only where we will be calling softfloat functions. We can use the -types.h in cpu.h for the few bits that are global. We also move the restore_snan_bit_mode into internal.h and include -helpers.h there. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* Include qemu-common.h exactly where neededMarkus Armbruster2019-06-121-1/+0
| | | | | | | | | | | | | | | | No header includes qemu-common.h after this commit, as prescribed by qemu-common.h's file comment. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190523143508.25387-5-armbru@redhat.com> [Rebased with conflicts resolved automatically, except for include/hw/arm/xlnx-zynqmp.h hw/arm/nrf51_soc.c hw/arm/msf2-soc.c block/qcow2-refcount.c block/qcow2-cluster.c block/qcow2-cache.c target/arm/cpu.h target/lm32/cpu.h target/m68k/cpu.h target/mips/cpu.h target/moxie/cpu.h target/nios2/cpu.h target/openrisc/cpu.h target/riscv/cpu.h target/tilegx/cpu.h target/tricore/cpu.h target/unicore32/cpu.h target/xtensa/cpu.h; bsd-user/main.c and net/tap-bsd.c fixed up]
* cpu: Remove CPU_COMMONRichard Henderson2019-06-101-2/+0
| | | | | | | | | | This macro is now always empty, so remove it. This leaves the entire contents of CPUArchState under the control of the guest architecture. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* cpu: Introduce CPUNegativeOffsetStateRichard Henderson2019-06-101-0/+1
| | | | | | | | | Nothing in there so far, but all of the plumbing done within the target ArchCPU state. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* cpu: Move ENV_OFFSET to exec/gen-icount.hRichard Henderson2019-06-101-1/+0
| | | | | | | | | Now that we have ArchCPU, we can define this generically, in the one place that needs it. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/mips: Use env_cpu, env_archcpuRichard Henderson2019-06-101-5/+0
| | | | | | | | | | Cleanup in the boilerplate that each target must define. Replace mips_env_get_cpu with env_archcpu. The combination CPU(mips_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson2019-06-101-2/+0
| | | | | | | | | Now that we have both ArchCPU and CPUArchState, we can define this generically instead of via macro in each target's cpu.h. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* cpu: Define ArchCPURichard Henderson2019-06-101-0/+1
| | | | | | | | For all targets, do this just before including exec/cpu-all.h. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* cpu: Define CPUArchState with typedefRichard Henderson2019-06-101-4/+2
| | | | | | | | For all targets, do this just before including exec/cpu-all.h. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Split out target/arch/cpu-param.hRichard Henderson2019-06-101-2/+1
| | | | | | | | | | | | | | | | For all targets, into this new file move TARGET_LONG_BITS, TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS, TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES. Include this new file from exec/cpu-defs.h. This now removes the somewhat odd requirement that target/arch/cpu.h defines TARGET_LONG_BITS before including exec/cpu-defs.h, so push the bulk of the includes within target/arch/cpu.h to the top. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/mips: realign comments to fix checkpatch warningsJules Irenge2019-05-261-12/+22
| | | | | | | | | | | Realign comments to fix warnings issued by checkpatc.pl tool "WARNING: Block comments use a leading /* on a separate line" within "target/mips/cpu.h" file. Signed-off-by: Jules Irenge <jbi.octave@gmail.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190413202818.13622-3-jbi.octave@gmail.com>
* target/mips: add or remove space to fix checkpatch errorsJules Irenge2019-05-261-81/+94
| | | | | | | | | | | | | | | | | Add or remove space to fix errors issued by checkpatch.pl tool "ERROR: spaces required around that..." "ERROR: space required after that..." "ERROR: space required before the open parenthesis" "ERROR: space required after that..." "ERROR: space prohibited between function name and open parenthesis" "ERROR: code indent should never use tabs" "ERROR: line over 90 characters" within "target/mips/cpu.h" file. Signed-off-by: Jules Irenge <jbi.octave@gmail.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190413202818.13622-2-jbi.octave@gmail.com>
* target: Simplify how the TARGET_cpu_list() printMarkus Armbruster2019-04-181-1/+1
| | | | | | | | | | | | | | | | | The various TARGET_cpu_list() take an fprintf()-like callback and a FILE * to pass to it. Their callers (vl.c's main() via list_cpus(), bsd-user/main.c's main(), linux-user/main.c's main()) all pass fprintf() and stdout. Thus, the flexibility provided by the (rather tiresome) indirection isn't actually used. Drop the callback, and call qemu_printf() instead. Calling printf() would also work, but would make the code unsuitable for monitor context without making it simpler. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190417191805.28198-10-armbru@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
* target/mips: introduce MTTCG-enabled buildsAleksandar Markovic2019-02-141-0/+2
| | | | | | | | | Introduce MTTCG-enabled QEMU builds for mips32, mipsn32, and mips64. Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Acked-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
* target/mips: reimplement SC instruction emulation and use cmpxchgLeon Alrae2019-02-141-4/+0
| | | | | | | | | | | | | | Completely rewrite conditional stores handling. Use cmpxchg. This eliminates need for separate implementations of SC instruction emulation for user and system emulation. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Acked-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* target/mips: compare virtual addresses in LL/SC sequenceLeon Alrae2019-02-141-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do only virtual addresses comaprisons in LL/SC sequence emulations. Until this patch, physical addresses had been compared in SC part of LL/SC sequence, even though such comparisons could be avoided. Getting rid of them allows throwing away SC helpers and having common SC implementations in user and system mode, avoiding the need for two separate implementations selected by #ifdef CONFIG_USER_ONLY. Correct guest software should not rely on LL/SC if they accesses the same physical address via different virtual addresses or if page mapping gets changed between LL/SC due to manipulating TLB entries. MIPS Instruction Set Manual clearly says that an RMW sequence must use the same address in the LL and SC (virtual address, physical address, cacheability and coherency attributes must be identical). Otherwise, the result of the SC is not predictable. This patch takes advantage of this fact and removes the virtual->physical address translation from SC helper. lladdr served as Coprocessor 0 LLAddr register which captures physical address of the most recent LL instruction, and also lladdr was used for comparison with following SC physical address. This patch changes the meaning of lladdr - now it will only keep the virtual address of the most recent LL. Additionally, CP0_LLAddr field is introduced which is the actual Coperocessor 0 LLAddr register that guest can access. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Acked-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Correct the second argument type of cpu_supports_isa()Aleksandar Markovic2019-01-241-1/+1
| | | | | | | | | | | | | "insn_flags" bitfield was expanded from 32-bit to 64-bit in commit f9c9cd63e3. However, this was not reflected on the second argument of the function cpu_supports_isa(). By chance, this did not create some wrong behavior, since the left-most halves of all instances of the second argument are currently all zeros. However, this is still a bug waiting to happen. Correct this by changing the type of the second argument to be always 64-bit. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Introduce 32 R5900 multimedia registersFredrik Noring2019-01-181-0/+3
| | | | | | | | | | The 32 R5900 128-bit registers are split into two 64-bit halves: the lower halves are the GPRs and the upper halves are accessible by the R5900-specific multimedia instructions. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add CP0 register MemoryMapIDAleksandar Markovic2019-01-181-0/+1
| | | | | | | | | Add CP0 register MemoryMapID. Only data field is added. The corresponding functionality will be added in future patches. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Amend preprocessor constants for CP0 registersAleksandar Markovic2019-01-181-32/+146
| | | | | | | | | | | | Correct existing CP0-related preprocessor constants (replace "CPO" with "CP0" (form letter "O" to digit "0", when needed). Besides, add preprocessor constants for CP0 subregisters. The names of the subregisters were chosen to be in sync with the table of corresponding assembler mnemonics found in the documentation for I6500 and I6400 (release 1.0). Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Update ITU to utilize SAARI and SAAR CP0 registersYongbok Kim2019-01-181-0/+5
| | | | | | | | Update ITU to utilize SAARI and SAAR CP0 registers. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Provide R/W access to SAARI and SAAR CP0 registersYongbok Kim2019-01-181-0/+1
| | | | | | | | Provide R/W access to SAARI and SAAR CP0 registers. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add fields for SAARI and SAAR CP0 registersYongbok Kim2019-01-181-2/+8
| | | | | | | | Add fields for SAARI and SAAR CP0 registers. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Add preprocessor constants for 32 major CP0 registersAleksandar Markovic2019-01-181-0/+32
| | | | | | | Add preprocessor constants for 32 major CP0 registers. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
* target/mips: Move comment containing summary of CP0 registersAleksandar Markovic2019-01-181-81/+84
| | | | | | | | | Move comment containing summary of CP0 registers. Checkpatch script reported some tabs in the resutling diff, so convert these tabs to spaces too. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>