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path: root/target/openrisc/cpu.h (follow)
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* target: Define TCG_GUEST_DEFAULT_MO in 'cpu-param.h'Philippe Mathieu-Daudé2024-04-261-2/+0
* include/exec: Implement cpu_mmu_index genericallyRichard Henderson2024-02-031-6/+0
* target/openrisc: Populate CPUClass.mmu_indexRichard Henderson2024-02-031-8/+2
* target/openrisc: Use generic cpu_list()Gavin Shan2024-01-051-3/+0
* target/openrisc: Declare QOM definitions in 'cpu-qom.h'Philippe Mathieu-Daudé2023-11-071-9/+1
* target: Unify QOM stylePhilippe Mathieu-Daudé2023-11-071-4/+0
* accel/tcg: Move CPUNegativeOffsetState into CPUStateRichard Henderson2023-10-031-1/+0
* other architectures: spelling fixesMichael Tokarev2023-07-251-1/+1
* target: Widen pc/cs_base in cpu_get_tb_cpu_stateAnton Johansson2023-06-261-3/+2
* target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemuPhilippe Mathieu-Daudé2023-02-271-1/+2
* target/openrisc: Convert to 3-phase resetPeter Maydell2022-12-161-2/+2
* target/openrisc: Enable MTTCGStafford Horne2022-09-041-0/+2
* Move CPU softfloat unions to cpu-float.hMarc-André Lureau2022-04-061-0/+1
* target: Use ArchCPU as interface to target CPUPhilippe Mathieu-Daudé2022-03-061-1/+1
* target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macroPhilippe Mathieu-Daudé2022-03-061-7/+1
* target: Use CPUArchState as interface to target-specific CPU statePhilippe Mathieu-Daudé2022-03-061-2/+1
* target: Use forward declared type instead of structure typePhilippe Mathieu-Daudé2022-03-061-2/+2
* target/openrisc: Make openrisc_cpu_tlb_fill sysemu onlyRichard Henderson2021-11-021-3/+4
* include/exec: Move cpu_signal_handler declarationRichard Henderson2021-09-211-2/+0
* target/openrisc: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé2021-09-141-2/+3
* target/openrisc: Move pic_cpu code into CPU object properPeter Maydell2020-12-151-1/+0
* qom: Remove module_obj_name parameter from OBJECT_DECLARE* macrosEduardo Habkost2020-09-181-1/+1
* Use OBJECT_DECLARE_TYPE where possibleEduardo Habkost2020-09-091-4/+2
* Use DECLARE_*CHECKER* macrosEduardo Habkost2020-09-091-6/+2
* Move QOM typedefs and add missing includesEduardo Habkost2020-09-091-4/+7
* Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell2020-03-191-1/+1
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| * cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell2020-03-171-1/+1
* | gdbstub: extend GByteArray to read register helpersAlex Bennée2020-03-171-1/+1
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* target/openrisc: Implement move to/from FPCSRRichard Henderson2019-09-041-0/+2
* target/openrisc: Add VR2 and AVR special processor registersRichard Henderson2019-09-041-4/+7
* target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu initRichard Henderson2019-09-041-4/+4
* target/openrisc: Make VR and PPC read-onlyRichard Henderson2019-09-041-3/+0
* hw/core: Move cpu.c, cpu.h from qom/ to hw/core/Markus Armbruster2019-08-211-1/+1
* migration: Move the VMStateDescription typedef to typedefs.hMarkus Armbruster2019-08-161-1/+1
* Include qemu-common.h exactly where neededMarkus Armbruster2019-06-121-1/+0
* cpu: Remove CPU_COMMONRichard Henderson2019-06-101-2/+0
* cpu: Introduce CPUNegativeOffsetStateRichard Henderson2019-06-101-1/+1
* cpu: Move ENV_OFFSET to exec/gen-icount.hRichard Henderson2019-06-101-1/+0
* target/openrisc: Use env_cpu, env_archcpuRichard Henderson2019-06-101-5/+0
* cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson2019-06-101-2/+0
* cpu: Define ArchCPURichard Henderson2019-06-101-0/+1
* cpu: Define CPUArchState with typedefRichard Henderson2019-06-101-2/+2
* tcg: Split out target/arch/cpu-param.hRichard Henderson2019-06-101-11/+3
* target/openrisc: Convert to CPUClass::tlb_fillRichard Henderson2019-05-101-2/+3
* target/openrisc: Fix LGPL information in the file headersThomas Huth2019-05-081-1/+1
* qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster2019-04-181-2/+1
* target: Simplify how the TARGET_cpu_list() printMarkus Armbruster2019-04-181-1/+1
* target/openrisc: Reorg tlb lookupRichard Henderson2018-07-031-8/+0
* target/openrisc: Increase the TLB sizeRichard Henderson2018-07-031-1/+1
* target/openrisc: Use identical sizes for ITLB and DTLBRichard Henderson2018-07-031-6/+4