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path: root/target/openrisc/sys_helper.c (follow)
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* system/cpus: rename qemu_mutex_lock_iothread() to bql_lock()Stefan Hajnoczi2024-01-081-8/+8
* tcg: Add insn_start_words to TCGContextRichard Henderson2023-06-051-1/+1
* *: Add missing includes of tcg/tcg.hRichard Henderson2023-06-051-0/+1
* target/openrisc: Allow fpcsr access in user modeStafford Horne2023-05-111-11/+34
* accel/tcg: Remove will_exit argument from cpu_restore_stateRichard Henderson2022-11-011-2/+2
* target/openrisc: Use cpu_unwind_state_data for mfsprRichard Henderson2022-11-011-2/+9
* target/openrisc: Always exit after mtspr npcRichard Henderson2022-11-011-1/+1
* target/openrisc: Interrupt handling fixesStafford Horne2022-09-041-0/+7
* target/openrisc: Enable MTTCGStafford Horne2022-09-041-1/+6
* Do not include sysemu/sysemu.h if it's not really necessaryThomas Huth2021-05-021-1/+0
* target/openrisc: Remove dead code attempting to check "is timer disabled"Peter Maydell2020-11-171-3/+0
* target/openrisc: Implement move to/from FPCSRRichard Henderson2019-09-041-5/+11
* target/openrisc: Add VR2 and AVR special processor registersRichard Henderson2019-09-041-0/+6
* target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu initRichard Henderson2019-09-041-2/+2
* target/openrisc: Make VR and PPC read-onlyRichard Henderson2019-09-041-9/+1
* general: Replace global smp variables with smp machine propertiesLike Xu2019-07-051-1/+5
* target/openrisc: Use env_cpu, env_archcpuRichard Henderson2019-06-101-4/+4
* target/openrisc: Fix LGPL version numberThomas Huth2019-01-301-1/+1
* target/openrisc: Fix writes to interrupt mask registerStafford Horne2018-07-031-1/+1
* target/openrisc: Use identical sizes for ITLB and DTLBRichard Henderson2018-07-031-8/+8
* target/openrisc: Fix cpu_mmu_indexRichard Henderson2018-07-031-4/+0
* target/openrisc: Fix tlb flushing in mtsprRichard Henderson2018-07-031-6/+15
* target/openrisc: Reduce tlb to a single dimensionRichard Henderson2018-07-031-10/+10
* target/openrisc: Remove indirect function calls for mmuRichard Henderson2018-07-031-15/+0
* target/openrisc: Merge tlb allocation into CPUOpenRISCStateRichard Henderson2018-07-031-14/+14
* target/openrisc: Form the spr index from tcgRichard Henderson2018-07-031-6/+3
* target/openrisc: Fix mtspr shadow gprsRichard Henderson2018-07-021-0/+1
* icount: fix cpu_restore_state_from_tb for non-tb-exit casesPavel Dovgalyuk2018-04-111-4/+4
* openrisc/cputimer: Perparation for MulticoreStafford Horne2017-10-211-2/+2
* target/openrisc: Make coreid and numcores variableStafford Horne2017-10-211-2/+3
* target/openrisc: Support non-busy idle state using PMR SPRStafford Horne2017-05-041-0/+13
* target/openrisc: implement shadow registersStafford Horne2017-05-041-0/+9
* target/openrisc: add numcores and coreid supportStafford Horne2017-05-041-0/+6
* target/openrisc: Implement EVBAR registerTim 'mithro' Ansell2017-04-211-0/+7
* target/openrisc: Tidy handling of delayed branchesRichard Henderson2017-02-141-1/+1
* target/openrisc: Tidy ppc/npc implementationRichard Henderson2017-02-141-28/+16
* target/openrisc: Represent MACHI:MACLO as a single unitRichard Henderson2017-02-141-0/+13
* target/openrisc: Keep SR_F in a separate variableRichard Henderson2017-02-141-3/+2
* cputlb: drop flush_global flag from tlb_flushAlex Bennée2017-01-131-1/+1
* Move target-* CPU file into a target/ folderThomas Huth2016-12-201-0/+288