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path: root/target/riscv/cpu_bits.h (follow)
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* target/riscv: FCSR doesn't contain vxrm and vxsatLIU Zhiwei2024-02-091-8/+0
* target/riscv: Implement optional CSR mcontext of debug Sdtrig extensionAlvin Chang2024-02-091-0/+7
* target/riscv: Add M-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal2023-11-071-0/+6
* target/riscv: Update CSR bits name for svadu extensionWeiwei Li2023-09-111-4/+4
* riscv: spelling fixesMichael Tokarev2023-09-081-2/+2
* riscv: Make sure an exception is raised if a pte is malformedAlexandre Ghiti2023-05-051-0/+1
* target/riscv: Add a general status enum for extensionsLIU Zhiwei2023-05-051-8/+4
* target/riscv: Use PRV_RESERVED instead of PRV_HWeiwei Li2023-05-051-1/+1
* target/riscv: Fix format for commentsWeiwei Li2023-05-051-1/+1
* target/riscv: Convert env->virt to a bool env->virt_enabledLIU Zhiwei2023-05-051-3/+0
* target/riscv: add support for Zcmt extensionWeiwei Li2023-05-051-0/+7
* target/riscv: Add csr support for svaduWeiwei Li2023-03-011-0/+4
* target/riscv: Add smstateen supportMayuresh Chitale2023-01-061-0/+37
* target/riscv: debug: Introduce tinfo CSRFrank Chang2022-09-271-0/+1
* target/riscv: Remove sideleg and sedelegRahul Pathak2022-09-271-2/+0
* target/riscv: Add sscofpmf extension supportAtish Patra2022-09-071-0/+55
* target/riscv: Add vstimecmp supportAtish Patra2022-09-071-0/+4
* target/riscv: Add stimecmp supportAtish Patra2022-09-071-0/+4
* target/riscv: Update default priority table for local interruptsAnup Patel2022-07-031-1/+1
* target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bitsAnup Patel2022-07-031-21/+3
* target/riscv: Implement mcountinhibit CSRAtish Patra2022-07-031-0/+4
* target/riscv: rvk: add CSR support for ZkrWeiwei Li2022-04-291-0/+9
* target/riscv: Add *envcfg* CSRs supportAtish Patra2022-04-221-0/+39
* target/riscv: Add support for mconfigptrAtish Patra2022-04-221-0/+1
* target/riscv: add support for svpbmt extensionWeiwei Li2022-02-161-0/+2
* target/riscv: add support for svnapot extensionWeiwei Li2022-02-161-0/+1
* target/riscv: Ignore reserved bits in PTE for RV64Guo Ren2022-02-161-0/+3
* target/riscv: Add defines for AIA CSRsAnup Patel2022-02-161-0/+119
* target/riscv: Implement hgeie and hgeip CSRsAnup Patel2022-02-161-0/+1
* target/riscv: Implement SGEIP bit in hip and hie CSRsAnup Patel2022-02-161-0/+3
* target/riscv: Enable uxl field writeLIU Zhiwei2022-01-211-0/+3
* target/riscv: actual functions to realize crs 128-bit insnsFrédéric Pétrot2022-01-081-0/+3
* target/riscv: rvv-1.0: add vlenb registerGreentime Hu2021-12-201-0/+1
* target/riscv: rvv-1.0: add vcsr registerLIU Zhiwei2021-12-201-0/+7
* target/riscv: rvv-1.0: add sstatus VS fieldLIU Zhiwei2021-12-201-0/+1
* target/riscv: rvv-1.0: add mstatus VS fieldLIU Zhiwei2021-12-201-0/+1
* target/riscv: remove force HS exceptionJose Martins2021-10-291-6/+0
* target/riscv: Add CSR defines for RISC-V PM extensionAlexey Baturo2021-10-281-0/+96
* target/riscv: Create RISCVMXL enumerationRichard Henderson2021-10-221-3/+5
* target/riscv: Remove some unused macrosAlistair Francis2021-10-221-8/+0
* target/riscv: csr: Rename HCOUNTEREN_CY and friendsBin Meng2021-09-211-4/+4
* target/riscv: Update the ePMP CSR addressAlistair Francis2021-09-211-2/+2
* target/riscv: fix wfi exception behaviorJose Martins2021-06-081-0/+1
* target/riscv: Remove the unused HSTATUS_WPRI macroAlistair Francis2021-05-111-6/+0
* target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis2021-05-111-11/+0
* target/riscv: Remove the hardcoded MSTATUS_SD macroAlistair Francis2021-05-111-10/+0
* target/riscv: Remove the hardcoded HGATP_MODE macroAlistair Francis2021-05-111-11/+0
* target/riscv: Remove the hardcoded SSTATUS_SD macroAlistair Francis2021-05-111-6/+0
* target/riscv: Define ePMP mseccfgHou Weiying2021-05-111-0/+3
* target/riscv: Convert the RISC-V exceptions to an enumAlistair Francis2021-05-111-21/+23